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Total properties:
19
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Patent #:
|
|
Issue Dt:
|
02/26/2013
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Application #:
|
10450615
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Filing Dt:
|
11/21/2003
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Publication #:
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Pub Dt:
|
04/07/2005
| | | | |
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Title:
|
PROCESSOR ARCHITECTURE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/16/2009
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Application #:
|
10521889
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Filing Dt:
|
05/25/2005
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Publication #:
|
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Pub Dt:
|
11/17/2005
| | | | |
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Title:
|
PROCESSOR ARRAY
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|
|
|
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Patent #:
|
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Issue Dt:
|
10/13/2009
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Application #:
|
10539337
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Filing Dt:
|
06/15/2005
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Publication #:
|
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Pub Dt:
|
07/27/2006
| | | | |
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Title:
|
ARRAY SYNCHRONISATION WITH COUNTERS
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|
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Patent #:
|
|
Issue Dt:
|
08/11/2009
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Application #:
|
10543370
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Filing Dt:
|
10/27/2005
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Publication #:
|
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Pub Dt:
|
07/13/2006
| | | | |
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Title:
|
PROCESSOR ARRAY INCLUDING DELAY ELEMENTS ASSOCIATED WITH PRIMARY BUS NODES
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Patent #:
|
|
Issue Dt:
|
07/26/2011
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Application #:
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10546616
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Filing Dt:
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07/31/2006
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Publication #:
|
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Pub Dt:
|
04/12/2007
| | | | |
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Title:
|
COMMUNICATIONS IN A PROCESSOR ARRAY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/11/2015
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Application #:
|
11981973
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Filing Dt:
|
11/01/2007
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|
Publication #:
|
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Pub Dt:
|
03/13/2008
| | | | |
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Title:
|
PROCESSOR ARCHITECTURE FOR PROCESSING VARIABLE LENGTH INSTRUCTION WORDS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/09/2011
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Application #:
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12070790
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Filing Dt:
|
02/21/2008
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|
Publication #:
|
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Pub Dt:
|
09/11/2008
| | | | |
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Title:
|
PROCESSOR ARCHITECTURE WITH SWITCH MATRICES FOR TRANSFERRING DATA ALONG BUSES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/15/2013
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Application #:
|
12264531
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Filing Dt:
|
11/04/2008
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|
Publication #:
|
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Pub Dt:
|
06/11/2009
| | | | |
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Title:
|
POWER CONTROL
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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12265152
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Filing Dt:
|
11/05/2008
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|
Publication #:
|
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Pub Dt:
|
06/11/2009
| | | | |
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Title:
|
GENERATING DEBUG INFORMATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/17/2012
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Application #:
|
12355002
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Filing Dt:
|
01/16/2009
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|
Publication #:
|
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Pub Dt:
|
07/23/2009
| | | | |
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Title:
|
FEMTOCELL DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/13/2011
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Application #:
|
12367814
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Filing Dt:
|
02/09/2009
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|
Publication #:
|
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Pub Dt:
|
08/20/2009
| | | | |
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Title:
|
SIGNAL ROUTING IN PROCESSOR ARRAYS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
01/08/2013
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Application #:
|
12368836
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Filing Dt:
|
02/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/20/2009
| | | | |
|
Title:
|
PROCESS PLACEMENT IN A PROCESSOR ARRAY
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12431750
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Filing Dt:
|
04/28/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
ALLOCATING RESOURCES IN A MULTICORE ENVIRONMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
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Application #:
|
12538311
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Filing Dt:
|
08/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
COMMUNICATION NETWORK
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12645689
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Filing Dt:
|
12/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/06/2011
| | | | |
|
Title:
|
Rake Receiver
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12773970
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Filing Dt:
|
05/05/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2010
| | | | |
|
Title:
|
Methods and Devices for Reducing Interference in an Uplink
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
12794128
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Filing Dt:
|
06/04/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
|
Method and Device in a Communication Network
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12794254
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Filing Dt:
|
06/04/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
|
METHOD AND DEVICE IN A COMMUNICATION NETWORK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13176381
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Filing Dt:
|
07/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
PROCESSOR ARCHITECTURE WITH SWITCH MATRICES FOR TRANSFERRING DATA ALONG BUSES
|
|
