Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 025990/0286 | |
| Pages: | 5 |
| | Recorded: | 03/21/2011 | | |
| Attorney Dkt #: | 0003 DIV1, DIV2, 0126 |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12316944
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Filing Dt:
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12/17/2008
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Title:
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JUNCTION FIELD EFFECT TRANSISTOR (JFET) STRUCTURE HAVING TOP-TO-BOTTOM GATE TIE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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12380490
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Filing Dt:
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02/26/2009
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Publication #:
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Pub Dt:
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08/27/2009
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Title:
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SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12380497
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Filing Dt:
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02/26/2009
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Publication #:
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Pub Dt:
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08/13/2009
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Title:
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SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE
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Assignee
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| 130 D KNOWLES DRIVE |
| LOS GATOS, CALIFORNIA 95032 |
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Correspondence name and address
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DEBBIE KUS
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130 D KNOWLES DRIVE
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LOS GATOS, CA 95032
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