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Total properties:
67
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Patent #:
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01/31/2006
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Application #:
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10118242
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Filing Dt:
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04/09/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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APPARATUS AND METHOD FOR HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10172996
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Filing Dt:
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06/18/2002
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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METHOD FOR DETECTING BUS CONTENTION FROM RTL DESCRIPTION
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10217535
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Filing Dt:
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08/14/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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METHOD FOR DETERMINING FAULT COVERAGE FROM RTL DESCRIPTION
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Issue Dt:
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07/11/2006
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Application #:
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10631755
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Filing Dt:
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08/01/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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IDENTIFICATION AND IMPLEMENTATION OF CLOCK GATING IN THE DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10695803
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
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Title:
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METHOD FOR CLOCK SYNCHRONIZATION VALIDATION IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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10711493
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
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03/23/2006
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Title:
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A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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12/19/2006
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10711971
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10/15/2004
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Publication #:
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Pub Dt:
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04/20/2006
| | | | |
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Title:
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A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC INSERTION AND CORRECTNESS VERIFICATION OF LEVEL SHIFTERS IN INTEGRATED CIRCUITS WITH MULTIPLE VOLTAGE DOMAINS
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05/08/2007
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10783091
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02/23/2004
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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PATTERN RECOGNITION IN AN INTEGRATED CIRCUIT DESIGN
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Issue Dt:
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09/02/2008
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Application #:
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11260225
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Filing Dt:
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10/28/2005
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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CHIP DEVELOPMENT SYSTEM ENABLED FOR THE HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
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03/17/2009
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11276819
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03/15/2006
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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METHOD FOR CLOCK SYNCHRONIZATION VALIDATION IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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06/09/2009
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11419624
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05/22/2006
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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A METHOD OF OPTIMIZATION OF CLOCK GATING IN INTEGRATED CIRCUIT DESIGNS
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Patent #:
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11/11/2008
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11423919
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06/13/2006
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Pub Dt:
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12/14/2006
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Title:
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BUS REPRESENTATION FOR EFFICIENT PHYSICAL SYNTHESIS OF INTEGRATED CIRCUIT DESIGNS
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Patent #:
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05/19/2009
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11426936
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06/27/2006
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Pub Dt:
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01/10/2008
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Title:
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METHOD FOR RECOGNIZING AND VERIFYING FIFO STRUCTURES IN INTEGRATED CIRCUIT DESIGNS
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04/12/2011
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11672919
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02/08/2007
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Title:
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METHODS FOR AUTOMATICALLY GENERATING ASSERTIONS
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01/19/2010
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11749090
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05/15/2007
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11/20/2008
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Title:
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METHOD FOR MODELING AND VERIFYING TIMING EXCEPTIONS
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02/01/2011
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11755764
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05/31/2007
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Pub Dt:
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12/04/2008
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Title:
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METHOD FOR CHECKING CONSTRAINTS EQUIVALENCE OF AN INTEGRATED CIRCUIT DESIGN
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05/10/2011
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11837174
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08/10/2007
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Pub Dt:
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02/12/2009
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Title:
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METHOD FOR COMPUTING POWER SAVINGS AND DETERMINING THE PREFERRED CLOCK GATING CIRCUIT OF AN INTEGRATED CIRCUIT DESIGN
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05/04/2010
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11959427
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12/18/2007
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04/24/2008
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METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
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10/18/2011
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12206473
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09/08/2008
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Publication #:
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03/11/2010
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Title:
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Patent #:
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NONE
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Application #:
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12634586
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12/09/2009
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04/08/2010
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Title:
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Systems and Methods for Generating Predicates and Assertions
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12/04/2012
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12649144
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12/29/2009
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10/09/2012
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12785986
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05/24/2010
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11/24/2011
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04/16/2013
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12910510
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10/22/2010
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04/28/2011
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05/21/2013
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12986644
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01/07/2011
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07/12/2012
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Title:
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SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT
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07/08/2014
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13178607
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07/08/2011
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01/10/2013
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Title:
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COMPUTER-AIDED DESIGN SYSTEM AND METHODS THEREOF FOR MERGING DESIGN CONSTRAINT FILES ACROSS OPERATIONAL MODES
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10/15/2013
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13209702
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08/15/2011
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02/16/2012
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Title:
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APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN
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12/10/2013
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13416856
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03/09/2012
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09/12/2013
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Title:
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HIERARCHICAL BOTTOM-UP CLOCK DOMAIN CROSSING VERIFICATION
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11/19/2013
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13433395
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03/29/2012
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07/18/2013
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Title:
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SYSTEM AND METHOD FOR INFERRING HIGHER LEVEL DESCRIPTIONS FROM RTL TOPOLOGY BASED ON NAMING SIMILARITIES AND DEPENDENCY
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02/18/2014
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13532175
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06/25/2012
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10/31/2013
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10/14/2014
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13625377
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09/24/2012
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03/27/2014
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CHARACTERIZATION BASED BUFFERING AND SIZING FOR SYSTEM PERFORMANCE OPTIMIZATION
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09/10/2013
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13645897
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10/05/2012
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09/15/2015
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13672477
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11/08/2012
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07/15/2014
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11/21/2012
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01/30/2014
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SYSTEMS AND METHODS FOR GENERATING A HIGHER LEVEL DESCRIPTION OF A CIRCUIT DESIGN BASED ON CONNECTIVITY STRENGTHS
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05/27/2014
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13756083
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01/31/2013
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SYSTEM AND METHOD FOR LARGE MULTIPLEXER IDENTIFICATION AND CREATION IN A DESIGN OF AN INTEGRATED CIRCUIT
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02/18/2014
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13766017
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02/13/2013
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SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN
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11/04/2014
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13783635
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03/04/2013
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09/04/2014
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METHOD FOR MEASURING ASSERTION DENSITY IN A SYSTEM OF VERIFYING INTEGRATED CIRCUIT DESIGN
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02/18/2014
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13791492
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03/08/2013
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SYSTEM AND METHOD FOR ABSTRACTION OF A CIRCUIT PORTION OF AN INTEGRATED CIRCUIT
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01/21/2014
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13828709
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03/14/2013
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SYSTEM AND METHOD FOR STRENGTHENING OF A CIRCUIT ELEMENT TO REDUCE AN INTEGRATED CIRCUIT'S POWER CONSUMPTION
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01/06/2015
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13829211
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03/14/2013
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09/18/2014
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SYSTEM AND METHOD FOR ALTERING CIRCUIT DESIGN HIERARCHY TO OPTIMIZE ROUTING AND POWER DISTRIBUTION
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06/17/2014
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13847938
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03/20/2013
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08/15/2013
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Title:
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METHOD AND SYSTEM THEREOF FOR OPTIMIZATION OF POWER CONSUMPTION OF SCAN CHAINS OF AN INTEGRATED CIRCUIT FOR TEST
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08/12/2014
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13851763
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03/27/2013
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03/17/2015
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04/16/2013
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09/18/2014
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SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION
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NONE
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13872303
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04/29/2013
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09/18/2014
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SYSTEM AND METHOD FOR FILTRATION OF ERROR REPORTS RESPECTIVE OF STATIC AND QUASI-STATIC SIGNALS WITHIN AN INTEGRATED CIRCUIT DESIGN
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10/07/2014
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13887596
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05/06/2013
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09/19/2013
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SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT
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06/03/2014
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13952024
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07/26/2013
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EFFICIENT APPARATUS AND METHOD FOR ANALYSIS OF RTL STRUCTURES THAT CAUSE PHYSICAL CONGESTION
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07/15/2014
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13954097
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07/30/2013
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07/22/2014
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13961758
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08/07/2013
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04/10/2014
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COMPUTER SYSTEM FOR GENERATING AN INTEGRATED AND UNIFIED VIEW OF IP-CORES FOR HIERARCHICAL ANALYSIS OF A SYSTEM ON CHIP (SOC) DESIGN
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05/20/2014
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14012734
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08/28/2013
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METHOD FOR CREATING PHYSICAL CONNECTIONS IN 3D INTEGRATED CIRCUITS
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12/08/2015
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10/07/2013
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02/06/2014
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09/16/2014
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10/16/2013
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10/02/2014
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08/19/2014
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14056094
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10/17/2013
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02/13/2014
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SYSTEM AND METHOD FOR INFERRING HIGHER LEVEL DESCRIPTIONS FROM RTL TOPOLOGY BASED ON NAMING SIMILARITIES AND DEPENDENCY
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03/18/2014
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14083109
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11/18/2013
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SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN
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03/17/2015
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14106374
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12/13/2013
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09/18/2014
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SYSTEM AND METHOD FOR STRENGTHENING OF A CIRCUIT ELEMENT TO REDUCE AN INTEGRATED CIRCUIT'S POWER CONSUMPTION
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NONE
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14181476
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02/14/2014
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08/20/2015
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SYSTEM AND METHOD FOR ABSTRACTION OF A CIRCUIT PORTION OF AN INTEGRATED CIRCUIT
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12/01/2015
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14184021
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02/19/2014
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08/20/2015
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METHOD AND APPARATUS USING FORMAL METHODS FOR CHECKING GENERATED-CLOCK TIMING DEFINITIONS
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Patent #:
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NONE
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Issue Dt:
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14196089
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Filing Dt:
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03/04/2014
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Publication #:
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Pub Dt:
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05/21/2015
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Title:
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SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN
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Patent #:
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08/02/2016
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Application #:
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14600234
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Filing Dt:
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01/20/2015
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Publication #:
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Pub Dt:
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12/10/2015
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Title:
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SYSTEM AND METHOD FOR REDUCING POWER OF A CIRCUIT USING CRITICAL SIGNAL ANALYSIS
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NONE
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Application #:
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14603188
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Filing Dt:
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01/22/2015
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Publication #:
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Pub Dt:
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07/28/2016
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Title:
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METHOD AND SYSTEM FOR SELECTING STIMULATION SIGNALS FOR POWER ESTIMATION
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Patent #:
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NONE
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Application #:
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14716422
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Filing Dt:
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05/19/2015
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11/24/2016
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Title:
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METHOD AND SYSTEM FOR CHECKING AND CORRECTING SHOOT-THROUGH IN RTL SIMULATION
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Patent #:
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Issue Dt:
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01/17/2017
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14745675
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06/22/2015
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Pub Dt:
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12/31/2015
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Title:
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SYSTEM AND METHOD FOR VIEWING AND MODIFYING CONFIGURABLE RTL MODULES
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Patent #:
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NONE
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14745700
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06/22/2015
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Pub Dt:
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12/31/2015
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Title:
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SYSTEM AND METHOD FOR GRADING AND SELECTING SIMULATION TESTS USING PROPERTY COVERAGE
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08/01/2017
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14790318
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07/02/2015
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09/08/2016
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Title:
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SYSTEM AND METHOD FOR NETLIST CLOCK DOMAIN CROSSING VERIFICATION
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08/01/2017
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14794549
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07/08/2015
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Pub Dt:
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10/13/2016
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Title:
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SYSTEM AND METHOD FOR REACTIVE INITIALIZATION BASED FORMAL VERIFICATION OF ELECTRONIC LOGIC DESIGN
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Patent #:
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08/20/2019
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14807676
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07/23/2015
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Pub Dt:
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01/26/2017
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Title:
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SYSTEM AND METHOD FOR MANAGING AND COMPOSING VERIFICATION ENGINES
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Patent #:
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NONE
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14812109
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07/29/2015
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Pub Dt:
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03/03/2016
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Title:
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SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW
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Patent #:
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06/04/2019
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14815202
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07/31/2015
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Pub Dt:
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10/06/2016
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Title:
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SYSTEM AND METHOD FOR POWER VERIFICATION USING EFFICIENT MERGING OF POWER STATE TABLES
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Patent #:
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NONE
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Application #:
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14815302
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07/31/2015
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Pub Dt:
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01/12/2017
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Title:
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SYSTEM AND METHOD FOR HIERARCHICAL POWER VERIFICATION
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