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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10109235
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Filing Dt:
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03/27/2002
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Title:
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MEMORY WORDLINE HARD MASK
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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10109516
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Filing Dt:
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03/27/2002
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Title:
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METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10126280
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Filing Dt:
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04/19/2002
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Title:
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MEMORY MANUFACTURING PROCESS USING DISPOSABLE ARC FOR WORDLINE FORMATION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10126326
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Filing Dt:
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04/19/2002
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Title:
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RELACS SHRINK METHOD APPLIED FOR SINGLE PRINT RESIST MASK FOR LDD OR BURIED BITLINE IMPLANTS USING CHEMICALLY AMPLIFIED DUV TYPE PHOTORESIST
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10128771
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Filing Dt:
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04/22/2002
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Title:
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SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10136173
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Filing Dt:
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05/01/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10151576
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Filing Dt:
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05/16/2002
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Title:
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MEMORY MANUFACTURING PROCESS USING BITLINE RAPID THERMAL ANNEAL
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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10155500
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Filing Dt:
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05/23/2002
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Title:
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METHOD AND SYSTEM FOR PROVIDING A POLYSILICON STRINGER MONITOR
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10217821
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Filing Dt:
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08/12/2002
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10223195
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10230729
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Filing Dt:
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08/29/2002
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Title:
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DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10243433
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Filing Dt:
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09/12/2002
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Title:
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PATH GATE DRIVER CIRCUIT
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10243792
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Filing Dt:
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09/12/2002
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Title:
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METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10264387
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Filing Dt:
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10/04/2002
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Title:
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GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10307189
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Filing Dt:
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11/29/2002
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Title:
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MEMORY WITH IMPROVED CHARGE-TRAPPING DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10308518
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Filing Dt:
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12/03/2002
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10358586
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Filing Dt:
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02/05/2003
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Title:
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ONO FABRICATION PROCESS FOR INCREASING OXYGEN CONTENT AT BOTTOM OXIDE-SUBSTRATE INTERFACE IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10359872
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Filing Dt:
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02/07/2003
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Title:
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METHOD OF FORMATION OF SEMICONDUCTOR RESISTANT TO HOT CARRIER INJECTION STRESS
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10382726
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Filing Dt:
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03/05/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION
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Patent #:
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Issue Dt:
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08/30/2005
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Application #:
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10387774
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Filing Dt:
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03/12/2003
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Title:
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MEMORY DEVICE HAVING REVERSE LDD
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10394565
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Filing Dt:
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03/21/2003
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Title:
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ALIGNMENT SYSTEM FOR PLANAR CHARGE TRAPPING DIELECTRIC MEMORY CELL LITHOGRAPHY
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10429447
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Filing Dt:
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05/05/2003
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Title:
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PROCESS FOR REDUCING HYDROGEN CONTAMINATION IN DIELECTRIC MATERIALS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10430582
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Filing Dt:
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05/06/2003
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Title:
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TRENCH SIDE WALL CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10431065
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Filing Dt:
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05/06/2003
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Title:
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METHOD TO OBTAIN TEMPERATURE INDEPENDENT PROGRAM THRESHOLD VOLTAGE DISTRIBUTION USING TEMPERATURE DEPENDENT VOLTAGE REFERENCE
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10431320
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Filing Dt:
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05/06/2003
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Title:
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NON-VOLATILE MEMORY READ CIRCUIT WITH END OF LIFE SIMULATION
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10658506
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Filing Dt:
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09/09/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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MEMORY DEVICE HAVING HIGH WORK FUNCTION GATE AND METHOD OF ERASING SAME
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10672093
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Filing Dt:
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09/26/2003
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10679774
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Filing Dt:
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10/06/2003
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Title:
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FLASH MEMORY DEVICE AND METHOD OF FABRICATION THEREOF INCLUDING A BOTTOM OXIDE LAYER WITH TWO REGIONS WITH DIFFERENT CONCENTRATIONS OF NITROGEN
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10731494
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Filing Dt:
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12/09/2003
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Title:
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PROCESS FOR FABRICATION OF SPACER LAYER WITH REDUCED HYDROGEN CONTENT IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10731659
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Filing Dt:
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12/09/2003
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Title:
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PROCESS FOR FABRICATION OF NITRIDE LAYER WITH REDUCED HYDROGEN CONTENT IN ONO STRUCTURE IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10758173
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Filing Dt:
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01/14/2004
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Title:
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ELECTROSTATIC DISCHARGE PERFORMANCE OF A SILICON STRUCTURE AND EFFICIENT USE OF AREA WITH ELECTROSTATIC DISCHARGE PROTECTIVE DEVICE UNDER THE PAD APPROACH AND ADJUSTMENT OF VIA CONFIGURATION THERETO TO CONTROL DRAIN JUNCTION RESISTANCE
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10795890
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Filing Dt:
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03/08/2004
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Title:
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SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10812703
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Filing Dt:
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03/30/2004
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Title:
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RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10860450
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Filing Dt:
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06/03/2004
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Title:
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METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10869286
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Filing Dt:
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06/16/2004
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Title:
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ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10883924
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Filing Dt:
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07/01/2004
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Title:
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FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10885284
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Filing Dt:
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07/06/2004
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Title:
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ARCHITECTURE FOR GENERATING ADAPTIVE ARBITRARY WAVEFORMS
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10889424
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Filing Dt:
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07/12/2004
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10896299
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Filing Dt:
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07/20/2004
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Title:
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METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10919119
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Filing Dt:
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08/16/2004
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Title:
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TEST STRUCTURE FOR CHARACTERIZING JUNCTION LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10919872
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Filing Dt:
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08/17/2004
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Title:
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METHOD TO IMPROVE YIELD AND SIMPLIFY OPERATION OF POLYMER MEMORY CELLS
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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11361277
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Filing Dt:
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02/24/2006
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Title:
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RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
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