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Reel/Frame:016147/0303   Pages: 5
Recorded: 01/13/2005
Attorney Dkt #:NSC1-M6500 [P06107]
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
07/04/2006
Application #:
10975171
Filing Dt:
10/28/2004
Title:
LAYOUT OPTIMIZATION OF INTEGRATED TRENCH VDMOS ARRAYS
Assignors
1
Exec Dt:
01/06/2005
2
Exec Dt:
01/06/2005
Assignee
1
2900 SEMICONDUCTOR DRIVE
SANTA CLARA, CALIFORNIA 95051
Correspondence name and address
MICHAEL J. POLLOCK
STALLMAN & POLLOCK LLP
353 SACRAMENTO STREET, SUITE 2200
SAN FRANCISCO, CA 94111

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