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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	019733/0312			Pages:	11
		Recorded:	08/22/2007
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 38

Patent #:	4459693	Issue Dt:	07/10/1984	Application #:	06342902	Filing Dt:	01/26/1982
Title:	METHOD OF AND APPARATUS FOR THE AUTOMATIC DIAGNOSIS OF THE FAILURE OF ELECTRICAL DEVICES CONNECTED TO COMMON BUS NODES AND THE LIKE

Patent #:	4620304	Issue Dt:	10/28/1986	Application #:	06710535	Filing Dt:	03/13/1985
Title:	METHOD OF AND APPARATUS FOR MULTIPLEXED AUTOMATIC TESTING OF ELECTRONIC CIRCUITS AND THE LIKE

Patent #:	4686391	Issue Dt:	08/11/1987	Application #:	06860819	Filing Dt:	05/08/1986
Title:	FAST-ACTING COMPARISON CIRCUIT

Patent #:	4864219	Issue Dt:	09/05/1989	Application #:	07027650	Filing Dt:	03/19/1987
Title:	METHOD AND APPARATUS FOR VERIFYING PROPER PLACEMENT OF INTEGRATED CIRCUITS ON CIRCUIT BOARDS

Patent #:	4782324	Issue Dt:	11/01/1988	Application #:	07047203	Filing Dt:	05/06/1987
Title:	DIGITAL SIGNAL SYNTHESIZER

Patent #:	4862069	Issue Dt:	08/29/1989	Application #:	07082054	Filing Dt:	08/05/1987
Title:	METHOD OF IN-CIRCUIT TESTING

Patent #:	4901315	Issue Dt:	02/13/1990	Application #:	07177067	Filing Dt:	04/04/1988
Title:	INTEGRATED DATA AND TIMING CIRCUITRY FOR AUTOMATIC CIRCUIT TESTER

Patent #:	4951283	Issue Dt:	08/21/1990	Application #:	07216917	Filing Dt:	07/08/1988
Title:	METHOD AND APPARATUS FOR IDENTIFYING DEFECTIVE BUS DEVICES

Patent #:	4977370	Issue Dt:	12/11/1990	Application #:	07280501	Filing Dt:	12/06/1988
Title:	APPARATUS & METHOD FOR CIRCUIT BOARD TESTING

Patent #:	4931742	Issue Dt:	06/05/1990	Application #:	07326966	Filing Dt:	03/22/1989
Title:	SELF-PROTECTING POWER BUS TESTING SYSTEM

Patent #:	5027298	Issue Dt:	06/25/1991	Application #:	07373993	Filing Dt:	06/29/1989
Title:	LOW-DEAD-TIME INTERVAL TIMER

Patent #:	5057775	Issue Dt:	10/15/1991	Application #:	07518453	Filing Dt:	05/04/1990
Title:	METHOD OF TESTING CONTROL MATRICES FOR FLAT-PANEL DISPLAYS

Patent #:	5103109	Issue Dt:	04/07/1992	Application #:	07547802	Filing Dt:	07/03/1990
Title:	GROUND-LOOP INTERRUPTION CIRCUIT

Patent #:	5172377	Issue Dt:	12/15/1992	Application #:	07578960	Filing Dt:	09/07/1990
Title:	METHOD FOR TESTING MIXED SCAN AND NON-SCAN CIRCUITRY

Patent #:	5128009	Issue Dt:	07/07/1992	Application #:	07621033	Filing Dt:	11/30/1990
Title:	PROCESS FOR REDUCING THE REFLECTIVITY OF SPUTTERED FILMS

Patent #:	5124636	Issue Dt:	06/23/1992	Application #:	07659755	Filing Dt:	02/22/1991
Title:	TESTER INTERCONNECT SYSTEM

Patent #:	5124638	Issue Dt:	06/23/1992	Application #:	07660277	Filing Dt:	02/22/1991
Title:	AUTOMATIC CIRCUIT TESTER EMPLOYING A THREE-DIMENSIONAL SWITCH-MATRIX LAYOUT

Patent #:	5101150	Issue Dt:	03/31/1992	Application #:	07660289	Filing Dt:	02/22/1991
Title:	AUTOMATIC CIRCUIT TESTER WITH SEPARATE INSTRUMENT AND SCANNER BUSES

Patent #:	5282211	Issue Dt:	01/25/1994	Application #:	07776850	Filing Dt:	10/15/1991
Title:	SLIP DETECTION DURING BIT-ERROR-RATE MEASUREMENT

Patent #:	5243272	Issue Dt:	09/07/1993	Application #:	07882217	Filing Dt:	05/13/1992
Title:	METHOD OF TESTING CONTROL MATRICES EMPLOYING DISTRIBUTED SOURCE RETURN

Patent #:	5414715	Issue Dt:	05/09/1995	Application #:	08014154	Filing Dt:	02/05/1993
Title:	METHOD FOR AUTOMATIC OPEN-CIRCUIT DETECTION

Patent #:	5426372	Issue Dt:	06/20/1995	Application #:	08100090	Filing Dt:	07/30/1993
Title:	PROBE FOR CAPACITIVE OPEN-CIRCUIT TESTS

Patent #:	5391993	Issue Dt:	02/21/1995	Application #:	08188385	Filing Dt:	01/27/1994
Title:	CAPACITIVE OPEN-CIRCUIT TEST EMPLOYING AN IMPROVED THRESHOLD DETERMINATION

Patent #:	5457380	Issue Dt:	10/10/1995	Application #:	08240981	Filing Dt:	05/11/1994
Title:	CIRCUIT-TEST FIXTURE THAT INCLUDES SHORTED-TOGETHER PROBES

Patent #:	5506510	Issue Dt:	04/09/1996	Application #:	08245477	Filing Dt:	05/18/1994
Title:	ADAPTIVE ALIGNMENT PROBE FIXTURE FOR CIRCUIT BOARD TESTER

Patent #:	5486753	Issue Dt:	01/23/1996	Application #:	08302227	Filing Dt:	09/08/1994
Title:	SIMULTANEOUS CAPACITIVE OPEN-CIRCUIT TESTING

Patent #:	5786697	Issue Dt:	07/28/1998	Application #:	08390065	Filing Dt:	02/17/1995
Title:	CAPACITIVE OPEN-CIRCUIT AND SHORT-CIRCUIT TESTS OF COMPONENT CONNECTIONS TO CIRCUIT BOARDS

Patent #:	5602490	Issue Dt:	02/11/1997	Application #:	08403472	Filing Dt:	03/14/1995
Title:	CONNECTOR FOR AUTOMATIC TEST EQUIPMENT

Patent #:	5736862	Issue Dt:	04/07/1998	Application #:	08493399	Filing Dt:	06/22/1995
Title:	SYSTEM FOR DETECTING FAULTS IN CONNECTIONS BETWEEN INTEGRATED CIRCUITS AND CIRCUIT BOARD TRACES

Patent #:	5811980	Issue Dt:	09/22/1998	Application #:	08517573	Filing Dt:	08/21/1995
Title:	TEST SYSTEM FOR DETERMINING THE ORIENTATION OF COMPONENTS ON A CIRCUIT BOARD

Patent #:	5615219	Issue Dt:	03/25/1997	Application #:	08552141	Filing Dt:	11/02/1995
Title:	SYSTEM AND METHOD OF PROGRAMMING A MULTISTATION TESTING SYSTEM

Patent #:	5745672	Issue Dt:	04/28/1998	Application #:	08564024	Filing Dt:	11/29/1995
Title:	MAIN MEMORY SYSTEM AND CHECKPOINTING PROTOCOL FOR A FAULT-TOLERANT COMPUTER SYSTEM USING A READ BUFFER

Patent #:	5861743	Issue Dt:	01/19/1999	Application #:	08576008	Filing Dt:	12/21/1995
Title:	HYBRID SCANNER FOR USE IN AN IMPROVED MDA TESTER

Patent #:	5548525	Issue Dt:	08/20/1996	Application #:	08580795	Filing Dt:	12/29/1995
Title:	METHOD AND APPARATUS FOR PIN ASSIGNMENT IN AUTOMATIC CIRCUIT TESTERS

Patent #:	6114848	Issue Dt:	09/05/2000	Application #:	09231001	Filing Dt:	01/14/1999
Title:	DIRECT-MEASUREMENT PROVISION OF SAFE BACKDRIVE LEVELS

Patent #:	6175230	Issue Dt:	01/16/2001	Application #:	09231049	Filing Dt:	01/14/1999
Title:	CIRCUIT-BOARD TESTER WITH BACKDRIVE-BASED BURST TIMING

Patent #:	6138143	Issue Dt:	10/24/2000	Application #:	09239100	Filing Dt:	01/28/1999
Title:	METHOD AND APPARATUS FOR ASYNCHRONOUS TRANSACTION PROCESSING

Patent #:	6393458	Issue Dt:	05/21/2002	Application #:	09289173	Filing Dt:	04/09/1999
Title:	METHOD AND APPARATUS FOR LOAD BALANCING IN A DISTRIBUTED OBJECT ARCHITECTURE

Assignor

BANK OF AMERICA

Exec Dt:

07/31/2007

Assignee

GENRAD, INC.

600 RIVERPARK DR.

N. READING, MASSACHUSETTS 01864

Correspondence name and address
	ATTN: CHET CEKALA
	TERADYNE, INC.
	600 RIVERPARK DR.
	600 RIVERPARK DR.
	N. READING, MA 01864

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