Total properties:
384
Page
3
of
4
Pages:
1 2 3 4
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11239791
|
Filing Dt:
|
09/29/2005
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
BI-DIRECTIONAL READ/PROGRAM NON-VOLATILE FLOATING GATE MEMORY ARRAY, AND METHOD OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11241582
|
Filing Dt:
|
09/30/2005
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
WORD LINE VOLTAGE BOOSTING CIRCUIT AND A MEMORY ARRAY INCORPORATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
11255905
|
Filing Dt:
|
10/20/2005
|
Publication #:
|
|
Pub Dt:
|
04/26/2007
| | | | |
Title:
|
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
11281182
|
Filing Dt:
|
11/16/2005
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
SELF-ALIGNED SPLIT-GATE NAND FLASH MEMORY AND FABRICATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11283195
|
Filing Dt:
|
11/18/2005
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
HIGH SPEED AND HIGH PRECISION SENSING FOR DIGITAL MULTILEVEL NON-VOLATILE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11303567
|
Filing Dt:
|
12/15/2005
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
STACKED GATE MEMORY CELL WITH ERASE TO GATE, ARRAY, AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11380595
|
Filing Dt:
|
04/27/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
PROCESS OF FABRICATING FLASH MEMORY WITH ENHANCED PROGRAM AND ERASE COUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11381948
|
Filing Dt:
|
05/05/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
NOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11407602
|
Filing Dt:
|
04/19/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
11487135
|
Filing Dt:
|
07/14/2006
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL BY CONTROLLING THE CHANNEL CURRENT DURING THE RISE PERIOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11516431
|
Filing Dt:
|
09/05/2006
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
BIDIRECTIONAL SPLIT GATE NAND FLASH MEMORY STRUCTURE AND ARRAY, METHOD OF PROGRAMMING, ERASING AND READING THEREOF, AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11520993
|
Filing Dt:
|
09/14/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
NON-PLANAR NON-VOLATILE MEMORY CELL WITH AN ERASE GATE, AN ARRAY THEREFOR, AND A METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11521162
|
Filing Dt:
|
09/14/2006
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
METHOD OF MAKING A BI-DIRECTIONAL READ/PROGRAM NON-VOLATILE FLOATING GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
11528748
|
Filing Dt:
|
09/27/2006
|
Publication #:
|
|
Pub Dt:
|
04/03/2008
| | | | |
Title:
|
POWER LINE COMPENSATION FOR FLASH MEMORY SENSE AMPLIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2009
|
Application #:
|
11535694
|
Filing Dt:
|
09/27/2006
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
NAND FLASH MEMORY WITH DENSELY PACKED MEMORY GATES AND FABRICATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11592104
|
Filing Dt:
|
11/01/2006
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
SELF-ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH SOURCE SIDE ERASE, AND A MEMORY ARRAY MADE THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
11599654
|
Filing Dt:
|
11/14/2006
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR STRAPPING TWO POLYSILICON LINES IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11602873
|
Filing Dt:
|
11/20/2006
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
SINGLE TRANSISTOR SENSING AND DOUBLE TRANSISTOR SENSING FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11652719
|
Filing Dt:
|
01/11/2007
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
MULTI-OPERATIONAL AMPLIFIER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11655901
|
Filing Dt:
|
01/19/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11707341
|
Filing Dt:
|
02/16/2007
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
METHOD FOR HANDLING A DEFECTIVE TOP GATE OF A SOURCE-SIDE INJECTION FLASH MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11707343
|
Filing Dt:
|
02/16/2007
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
11717922
|
Filing Dt:
|
03/13/2007
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
HIGH-SPEED AND LOW-POWER DIFFERENTIAL NON-VOLATILE CONTENT ADDRESSABLE MEMORY CELL AND ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11726913
|
Filing Dt:
|
03/22/2007
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
WIDE DYNAMIC RANGE AND HIGH SPEED VOLTAGE MODE SENSING FOR A MULTILEVEL DIGITAL NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
11772080
|
Filing Dt:
|
06/29/2007
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11775851
|
Filing Dt:
|
07/10/2007
|
Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
Title:
|
NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11777895
|
Filing Dt:
|
07/13/2007
|
Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
Title:
|
SUB VOLT FLASH MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11797159
|
Filing Dt:
|
05/01/2007
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
ASSEMBLY OF SIM CARD AND RFID ANTENNA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
11805765
|
Filing Dt:
|
05/23/2007
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
CHARGE PUMP SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11807131
|
Filing Dt:
|
05/25/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHOD OF MAKING PHASE CHANGE MEMORY DEVICE EMPLOYING THERMALLY INSULATING VOIDS AND SLOPED TRENCH
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11808151
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/20/2007
| | | | |
Title:
|
CHIPSET FOR MOBILE WALLET SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11810714
|
Filing Dt:
|
06/06/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SPLIT GATE NAND FLASH MEMORY STRUCTURE AND ARRAY, METHOD OF PROGRAMMING, ERASING AND READING THEREOF, AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11828213
|
Filing Dt:
|
07/25/2007
|
Title:
|
BIDIRECTIONAL NONVOLATILE MEMORY CELL HAVING CHARGE TRAPPING LAYER IN TRENCH AND AN ARRAY OF SUCH MEMORY CELLS, AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11830720
|
Filing Dt:
|
07/30/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
MULTI-OPERATIONAL AMPLIFIER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11855801
|
Filing Dt:
|
09/14/2007
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
Title:
|
INDEPENDENT BI-DIRECTIONAL MARGIN CONTROL PER LEVEL AND INDEPENDENTLY EXPANDABLE REFERENCE CELL LEVELS FOR FLASH MEMORY SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11923515
|
Filing Dt:
|
10/24/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
ARRAY OF CONTACTLESS NON-VOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11941964
|
Filing Dt:
|
11/18/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
FAST VOLTAGE REGULATORS FOR CHARGE PUMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11942665
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
Title:
|
SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
11950331
|
Filing Dt:
|
12/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH PROGRAM/ERASE AND SELECT GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11950345
|
Filing Dt:
|
12/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH PROGRAM/ERASE AND SELECT GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11953754
|
Filing Dt:
|
12/10/2007
|
Publication #:
|
|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
TEST CIRCUIT AND METHOD FOR MULTILEVEL CELL FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11963552
|
Filing Dt:
|
12/21/2007
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING HIGH SPEED SERIAL INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
12027654
|
Filing Dt:
|
02/07/2008
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
Title:
|
METHOD FOR ERASING A FLASH MEMORY CELL OR AN ARRAY OF SUCH CELLS HAVING IMPROVED ERASE COUPLING RATIO
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12027916
|
Filing Dt:
|
02/07/2008
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHOD OF TRIMMING SEMICONDUCTOR ELEMENTS WITH ELECTRICAL RESISTANCE FEEDBACK
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
12100406
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
STORAGE ELEMENT FOR CONTROLLING A LOGIC CIRCUIT, AND A LOGIC DEVICE HAVING AN ARRAY OF SUCH STORAGE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12126853
|
Filing Dt:
|
05/23/2008
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR READING AND PROGRAMMING A NON-VOLATILE MEMORY CELL IN A VIRTUAL GROUND ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12131008
|
Filing Dt:
|
05/30/2008
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR SYSTEMATIC AND RANDOM VARIATION AND MISMATCH COMPENSATION FOR MULTILEVEL FLASH MEMORY OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12176281
|
Filing Dt:
|
07/18/2008
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
HIGH-SPEED AND LOW-POWER DIFFERENTIAL NON-VOLATILE CONTENT ADDRESSABLE MEMORY CELL AND ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12200930
|
Filing Dt:
|
08/28/2008
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
Title:
|
FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12266443
|
Filing Dt:
|
11/06/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
LANDING PAD FOR USE AS A CONTACT TO A CONDUCTIVE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2010
|
Application #:
|
12267519
|
Filing Dt:
|
11/07/2008
|
Publication #:
|
|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
FLASH MEMORY ARRAY WITH A TOP GATE LINE DYNAMICALLY COUPLED TO A WORD LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12275191
|
Filing Dt:
|
11/20/2008
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12324816
|
Filing Dt:
|
11/26/2008
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
Title:
|
NON-VOLATILE MEMORY CELL WITH SELF ALIGNED FLOATING AND ERASE GATES, AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12327114
|
Filing Dt:
|
12/03/2008
|
Publication #:
|
|
Pub Dt:
|
06/03/2010
| | | | |
Title:
|
NON-VOLATILE MEMORY CELL WITH BURIED SELECT GATE, AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12340571
|
Filing Dt:
|
12/19/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
FAST VOLTAGE REGULATORS FOR CHARGE PUMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12362106
|
Filing Dt:
|
01/29/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
12398155
|
Filing Dt:
|
03/04/2009
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
ARRAY OF NON-VOLATILE MEMORY CELLS INCLUDING EMBEDDED LOCAL AND GLOBAL REFERENCE CELLS AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12468762
|
Filing Dt:
|
05/19/2009
|
Title:
|
PROGRAMMABLE INTEGRATED CIRCUIT HAVING BUILT IN TEST CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12493240
|
Filing Dt:
|
06/28/2009
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12507783
|
Filing Dt:
|
07/22/2009
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12542605
|
Filing Dt:
|
08/17/2009
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
Title:
|
METHOD AND APPARATUS FOR STRAPPING TWO POLYSILICON LINES IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
12555756
|
Filing Dt:
|
09/08/2009
|
Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
Title:
|
FIN-FET NON-VOLATILE MEMORY CELL, AND AN ARRAY AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12558285
|
Filing Dt:
|
09/11/2009
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12569832
|
Filing Dt:
|
09/29/2009
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
CHARGE PUMP CIRCUIT AND A NOVEL CAPACITOR FOR A MEMORY INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12581783
|
Filing Dt:
|
10/19/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12618632
|
Filing Dt:
|
11/13/2009
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
Title:
|
SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12623259
|
Filing Dt:
|
11/20/2009
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING HIGH SPEED SERIAL INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
12629302
|
Filing Dt:
|
12/02/2009
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
Title:
|
METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12637365
|
Filing Dt:
|
12/14/2009
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
Title:
|
TEST CIRCUIT AND METHOD FOR MULTILEVEL CELL FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
12638827
|
Filing Dt:
|
12/15/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
PANEL BASED LEAD FRAME PACKAGING METHOD AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12645337
|
Filing Dt:
|
12/22/2009
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
METHOD FOR ERASING A FLASH MEMORY CELL OR AN ARRAY OF SUCH CELLS HAVING IMPROVED ERASE COUPLING RATIO
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12725370
|
Filing Dt:
|
03/16/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE WITH PLURAL REFERENCE CELLS, AND METHOD OF SETTING THE REFERENCE CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
12726249
|
Filing Dt:
|
03/17/2010
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
FAST START CHARGE PUMP FOR VOLTAGE REGULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12750628
|
Filing Dt:
|
03/30/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12762825
|
Filing Dt:
|
04/19/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
METHOD OF TESTING AN INTEGRATED CIRCUIT DIE, AND AN INTEGRATED CIRCUIT DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12766682
|
Filing Dt:
|
04/23/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
POWER LINE COMPENSATION FOR FLASH MEMORY SENSE AMPLIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2012
|
Application #:
|
12773811
|
Filing Dt:
|
05/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
12872351
|
Filing Dt:
|
08/31/2010
|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
Title:
|
SPLIT GATE NAND FLASH MEMORY STRUCTURE AND ARRAY, METHOD OF PROGRAMMING, ERASING AND READING THEREOF, AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
12887956
|
Filing Dt:
|
09/22/2010
|
Title:
|
NON-VOLATILE MEMORY ELEMENT INTEGRATABLE WITH STANDARD CMOS CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12889653
|
Filing Dt:
|
09/24/2010
|
Title:
|
MULTIPLE TIME PROGRAMMABLE NON-VOLATILE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12889659
|
Filing Dt:
|
09/24/2010
|
Title:
|
METHOD OF SENSING A PROGRAMMABLE NON-VOLATILE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12899120
|
Filing Dt:
|
10/06/2010
|
Publication #:
|
|
Pub Dt:
|
01/27/2011
| | | | |
Title:
|
TEST CIRCUIT AND METHOD FOR MULTILEVEL CELL FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
12947719
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
Title:
|
INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12961193
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2013
|
Application #:
|
12961458
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
Non-volatile memory systems and methods including page read and/or configuration features
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
12962343
|
Filing Dt:
|
12/07/2010
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
12965504
|
Filing Dt:
|
12/10/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
ARRAY OF NON-VOLATILE MEMORY CELLS INCLUDING EMBEDDED LOCAL AND GLOBAL REFERENCE CELLS AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
12972974
|
Filing Dt:
|
12/20/2010
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12980209
|
Filing Dt:
|
12/28/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
SUB VOLT FLASH MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2011
|
Application #:
|
12987906
|
Filing Dt:
|
01/10/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
FAST VOLTAGE REGULATORS FOR CHARGE PUMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
13070405
|
Filing Dt:
|
03/23/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
CHARGE PUMP SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13097766
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
HIGH ENDURANCE NON-VOLATILE MEMORY CELL AND ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13172599
|
Filing Dt:
|
06/29/2011
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
SUB VOLT FLASH MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
13286166
|
Filing Dt:
|
10/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/23/2012
| | | | |
Title:
|
SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13286843
|
Filing Dt:
|
11/01/2011
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
Low Voltage, Low Power Bandgap Circuit
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13286933
|
Filing Dt:
|
11/01/2011
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
METHOD OF PROGRAMMING A SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELL HAVING A SEPARATE ERASE GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13286969
|
Filing Dt:
|
11/01/2011
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
MIXED VOLTAGE NON-VOLATILE MEMORY INTEGRATED CIRCUIT WITH POWER SAVING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13293056
|
Filing Dt:
|
11/09/2011
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
METHOD OF TESTING DATA RETENTION OF A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13299320
|
Filing Dt:
|
11/17/2011
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
ARRAY OF SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELLS HAVING IMPROVED STRAPPING OF THE COUPLING GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
13306950
|
Filing Dt:
|
11/29/2011
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
Title:
|
FAST VOLTAGE REGULATORS FOR CHARGE PUMPS
|
|