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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:055029/0317   Pages: 5
Recorded: 01/26/2021
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 17
1
Patent #:
Issue Dt:
02/03/2004
Application #:
09589840
Filing Dt:
06/08/2000
Title:
MACRO-CELL FLIP-FLOP WITH SCAN-IN INPUT
2
Patent #:
Issue Dt:
10/26/2004
Application #:
09621717
Filing Dt:
07/24/2000
Title:
STRUCTURE AND METHOD FOR MONITORING A SEMICONDUCTOR PROCESS, AND METHOD OF MAKING SUCH A STRUCTURE
3
Patent #:
Issue Dt:
03/26/2002
Application #:
09627567
Filing Dt:
07/28/2000
Title:
Use of an etch to reduce the thickness and round the edges of a resist mask during the creation of a memory cell
4
Patent #:
Issue Dt:
03/26/2002
Application #:
09648361
Filing Dt:
08/25/2000
Title:
METHOD OF FORMING ONO FLASH MEMORY DEVICES USING LOW ENERGY NITROGEN IMPLANTATION
5
Patent #:
Issue Dt:
07/09/2002
Application #:
09651684
Filing Dt:
08/30/2000
Title:
Semiconductor structure
6
Patent #:
Issue Dt:
03/04/2003
Application #:
09665916
Filing Dt:
09/20/2000
Title:
NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER
7
Patent #:
Issue Dt:
01/18/2005
Application #:
09774323
Filing Dt:
01/31/2001
Title:
METHOD FOR IMPROVING DIELECTRIC POLISHING
8
Patent #:
Issue Dt:
06/03/2003
Application #:
09884204
Filing Dt:
06/19/2001
Title:
METHOD OF FORMING ZERO MARKS
9
Patent #:
Issue Dt:
08/05/2003
Application #:
09909109
Filing Dt:
07/18/2001
Title:
CONFIGURING DIGITAL FUNCTIONS IN A DIGITAL CONFIGURABLE MACRO ARCHITECTURE
10
Patent #:
Issue Dt:
03/23/2004
Application #:
09927134
Filing Dt:
08/10/2001
Title:
PROCESS FOR TREATING ONO DIELECTRIC FILM OF A FLOATING GATE MEMORY CELL
11
Patent #:
Issue Dt:
01/18/2005
Application #:
09944234
Filing Dt:
08/31/2001
Title:
CMP PROCESS
12
Patent #:
Issue Dt:
03/02/2004
Application #:
09989574
Filing Dt:
11/19/2001
Title:
METHOD AND SYSTEM FOR USING A GRAPHICS USER INTERFACE FOR PROGRAMMING AN ELECTRONIC DEVICE
13
Patent #:
Issue Dt:
10/26/2004
Application #:
10045354
Filing Dt:
11/07/2001
Title:
INNOVATIVE METHOD OF HARD MASK REMOVAL
14
Patent #:
Issue Dt:
08/22/2006
Application #:
10142963
Filing Dt:
05/13/2002
Title:
METHOD OF FORMING NITRIDED OXIDE IN A HOT WALL SINGLE WAFER FURNACE
15
Patent #:
Issue Dt:
05/11/2004
Application #:
10160050
Filing Dt:
06/04/2002
Publication #:
Pub Dt:
10/17/2002
Title:
METHOD OF DRIVING A SEMICONDUCTOR MEMORY
16
Patent #:
Issue Dt:
09/14/2004
Application #:
10269391
Filing Dt:
10/11/2002
Title:
MEMORY DEVICE PROVIDING ASYNCHRONOUS AND SYNCHRONOUS DATA TRANSFER
17
Patent #:
Issue Dt:
03/22/2005
Application #:
10323002
Filing Dt:
12/18/2002
Title:
FABRICATION OF A BIPOLAR TRANSISTOR USING A SACRIFICIAL EMITTER
Assignor
1
Exec Dt:
11/16/2020
Assignee
1
9901 BRODIE LANE, SUITE 160 PMB 784
AUSTIN, TEXAS 78748
Correspondence name and address
SPEARHEAD IP LLC
9901 BRODIE LANE, SUITE 160 PMB 784
AUSTIN, TX 78748

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