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Patent Assignment Details

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Reel/Frame:	031576/0320			Pages:	10
		Recorded:	11/11/2013
Attorney Dkt #:	4999-0001
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	7139985	Issue Dt:	11/21/2006	Application #:	10871311	Filing Dt:	06/18/2004
Publication #:	US20050055657	Pub Dt:	03/10/2005
Title:	DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS

Patent #:	7206870	Issue Dt:	04/17/2007	Application #:	10871347	Filing Dt:	06/18/2004
Publication #:	US20050005250	Pub Dt:	01/06/2005
Title:	DATA INTERFACE REGISTER STRUCTURE WITH REGISTERS FOR DATA, VALIDITY, GROUP MEMBERSHIP INDICATOR, AND READY TO ACCEPT NEXT MEMBER SIGNAL

Patent #:	7409533	Issue Dt:	08/05/2008	Application #:	11326701	Filing Dt:	01/06/2006
Publication #:	US20060117275	Pub Dt:	06/01/2006
Title:	ASYNCHRONOUS COMMUNICATION AMONG HARDWARE OBJECT NODES IN IC WITH RECEIVE AND SEND PORTS PROTOCOL REGISTERS USING TEMPORARY REGISTER BYPASS SELECT FOR VALIDITY INFORMATION

Patent #:	7801033	Issue Dt:	09/21/2010	Application #:	11340957	Filing Dt:	01/27/2006
Publication #:	US20070025382	Pub Dt:	02/01/2007
Title:	SYSTEM OF VIRTUAL DATA CHANNELS IN AN INTEGRATED CIRCUIT

Patent #:	7945803	Issue Dt:	05/17/2011	Application #:	11460231	Filing Dt:	07/26/2006
Publication #:	US20070064852	Pub Dt:	03/22/2007
Title:	CLOCK GENERATION FOR MULTIPLE CLOCK DOMAINS

Patent #:	7406584	Issue Dt:	07/29/2008	Application #:	11466083	Filing Dt:	08/21/2006
Publication #:	US20060282812	Pub Dt:	12/14/2006
Title:	IC COMPRISING NETWORK OF MICROPROCESSORS COMMUNICATING DATA MESSAGES ALONG ASYNCHRONOUS CHANNEL SEGMENTS USING PORTS INCLUDING VALIDITY AND ACCEPT SIGNAL REGISTERS AND WITH SPLIT/JOIN CAPABILITY

Patent #:	7673275	Issue Dt:	03/02/2010	Application #:	11466337	Filing Dt:	08/22/2006
Publication #:	US20060282813	Pub Dt:	12/14/2006
Title:	DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS

Patent #:	7577874	Issue Dt:	08/18/2009	Application #:	11673986	Filing Dt:	02/12/2007
Publication #:	US20070180323	Pub Dt:	08/02/2007
Title:	INTERACTIVE DEBUG SYSTEM FOR MULTIPROCESSOR ARRAY

Patent #:	7805638	Issue Dt:	09/28/2010	Application #:	11676206	Filing Dt:	02/16/2007
Publication #:	US20070180334	Pub Dt:	08/02/2007
Title:	MULTI-FREQUENCY DEBUG NETWORK FOR A MULTIPROCESSOR ARRAY

Patent #:	8103866	Issue Dt:	01/24/2012	Application #:	12018062	Filing Dt:	01/22/2008
Publication #:	US20080229093	Pub Dt:	09/18/2008
Title:	SYSTEM FOR RECONFIGURING A PROCESSOR ARRAY

Patent #:	8498493	Issue Dt:	07/30/2013	Application #:	12477012	Filing Dt:	06/02/2009
Title:	DIRECTIONAL CROSS HAIR SEARCH SYSTEM AND METHOD FOR DETERMINING A PREFERRED MOTION VECTOR

Patent #:	8922573	Issue Dt:	12/30/2014	Application #:	12502927	Filing Dt:	07/14/2009
Title:	VIDEO NON-BUFFERED LINE MEMORY

Patent #:	8498334	Issue Dt:	07/30/2013	Application #:	12699799	Filing Dt:	02/03/2010
Title:	METHOD AND SYSTEM FOR STAGGERED PARALLELIZED VIDEO DECODING

Assignor

Exec Dt:

01/17/2013

Assignee

GENESIS HOUSE, INNOVATION CENTRE & PINNACLE HOUSE

HOME PARK ESTATE, KINGS LANGLEY

HERTFORDSHIRE, UNITED KINGDOM WD4 8LZ

Correspondence name and address
	KEVIN S. ROSS
	MARGER JOHNSON & MCCOLLOM PC
	210 SW MORRISON STREET, SUITE 400
	PORTLAND, OR 97204

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