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Reel/Frame:023957/0323   Pages: 4
Recorded: 02/17/2010
Attorney Dkt #:Z9995.0211
Conveyance: SUBMISSION TO CONFIRM THAT ASSIGNMENT AT REEL/FRAME 023245/0186 WAS ERRONEOUSLY RECORDED AGAINST THE IDENTIFIED PATENTS/APPLICATION.
Total properties: 26
1
Patent #:
Issue Dt:
05/18/2004
Application #:
09089445
Filing Dt:
06/03/1998
Title:
DRAM CAPACITOR FORMULATION USING A DOUBLE-SIDED ELECTRODE
2
Patent #:
Issue Dt:
08/01/2000
Application #:
09137155
Filing Dt:
08/20/1998
Title:
PHOTO-ASSISTED REMOTE PLASMA APPARATUS AND METHOD
3
Patent #:
Issue Dt:
09/26/2000
Application #:
09141144
Filing Dt:
08/27/1998
Title:
METHOD AND APPARATUS FOR ULTRASONIC WET ETCHING OF SILICON
4
Patent #:
Issue Dt:
11/04/2003
Application #:
09146519
Filing Dt:
09/03/1998
Title:
SYSTEM FOR FILLING OPENINGS IN SEMICONDUCTOR PRODUCTS
5
Patent #:
Issue Dt:
03/13/2001
Application #:
09178480
Filing Dt:
10/26/1998
Title:
HEAT SINK FOR CHIP STACKING APPLICATIONS
6
Patent #:
Issue Dt:
02/29/2000
Application #:
09178682
Filing Dt:
10/26/1998
Title:
PRINTED CIRCUIT BOARD WITH INTERGRATED HEAT SINK
7
Patent #:
Issue Dt:
05/21/2002
Application #:
09196437
Filing Dt:
11/20/1998
Title:
POLYCIDE STRUCTURE AND METHOD FOR FORMING POLYCIDE STRUCTURE
8
Patent #:
Issue Dt:
09/02/2003
Application #:
09240395
Filing Dt:
01/29/1999
Title:
FABRICATION OF SEMICONDUCTOR DEVICES WITH TRANSITION METAL BORIDE FILMS AS DIFFUSION BARRIERS
9
Patent #:
Issue Dt:
04/24/2001
Application #:
09285668
Filing Dt:
04/05/1999
Title:
METHOD OF FORMING A METAL SEED LAYER FOR SUBSEQUENT PLATING
10
Patent #:
Issue Dt:
10/23/2001
Application #:
09342212
Filing Dt:
06/29/1999
Title:
METHOD FOR FORMING WIRING WITH EXTREMELY LOW PARASITIC CAPACITANCE
11
Patent #:
Issue Dt:
03/06/2001
Application #:
09376232
Filing Dt:
08/18/1999
Title:
PASSIVATION OF SIDEWALLS OF A WORD LINE STACK
12
Patent #:
Issue Dt:
05/06/2003
Application #:
09377070
Filing Dt:
08/19/1999
Title:
METHOD OF REMOVING FREE HALOGEN FROM A HALOGENATED POLYMER INSULATING LAYER OF A SEMICONDUCTOR DEVICE
13
Patent #:
Issue Dt:
03/25/2003
Application #:
09385379
Filing Dt:
08/30/1999
Title:
SYSTEM FOR DISTRIBUTING CLOCK SIGNAL WITH A RISK RATE SUCH THAT SIGNALS APPEARING AT FIRST AND SECOND OUTPUT TERMINALS HAVE SUBSTANTIALLY NO SIGNAL SKEW
14
Patent #:
Issue Dt:
04/17/2001
Application #:
09385381
Filing Dt:
08/30/1999
Title:
ELECTROPLATING APPARATUS AND METHOD
15
Patent #:
Issue Dt:
11/19/2002
Application #:
09386313
Filing Dt:
08/13/1999
Title:
VERTICAL SUB-MICRON CMOS TRANSISTORS ON (110), (111), (311), (511), AND HIGHER ORDER SURFACES OF BULK, SOI AND THIN FILM STRUCTURES AND METHOD OF FORMING SAME
16
Patent #:
Issue Dt:
08/20/2002
Application #:
09386315
Filing Dt:
08/31/1999
Title:
METHOD FOR FABRICATING CMOS TRANSISTORS HAVING MATCHING CHARACTERISTICS AND APPARATUS FORMED THEREBY
17
Patent #:
Issue Dt:
06/12/2001
Application #:
09386320
Filing Dt:
08/31/1999
Title:
TEST HEAD ASSEMBLY UTILIZING REPLACEABLE SILICON CONTACT
18
Patent #:
Issue Dt:
08/20/2002
Application #:
09639090
Filing Dt:
08/16/2000
Title:
METHOD FOR MAKING SHALLOW TRENCHES FOR ISOLATION
19
Patent #:
Issue Dt:
09/17/2002
Application #:
09648465
Filing Dt:
08/28/2000
Title:
DAMASCENE STRUCTURE AND METHOD OF MAKING
20
Patent #:
Issue Dt:
09/09/2003
Application #:
09653560
Filing Dt:
08/31/2000
Title:
SUBTRACTIVE METALLIZATION STRUCTURE AND METHOD OF MAKING
21
Patent #:
Issue Dt:
05/13/2003
Application #:
09805909
Filing Dt:
03/15/2001
Publication #:
Pub Dt:
09/19/2002
Title:
MONOTONIC DYNAMIC STATIC PSEUDO-NMOS LOGIC CIRCUITS
22
Patent #:
Issue Dt:
08/20/2002
Application #:
09808139
Filing Dt:
03/15/2001
Title:
CLOCKED DIFFERENTIAL CASCODE VOLTAGE SWITCH WITH PASS GATE LOGIC
23
Patent #:
Issue Dt:
10/08/2002
Application #:
09878432
Filing Dt:
06/12/2001
Title:
CLOCKED PASS TRANSISTOR AND COMPLEMENTARY PASS TRANSISTOR LOGIC CIRCUITS
24
Patent #:
Issue Dt:
12/17/2002
Application #:
09938615
Filing Dt:
08/27/2001
Title:
REGULATOR CIRCUIT FOR INDEPENDENT ADJUSTMENT OF PUMPS IN MULTIPLE MODES OF OPERATION
25
Patent #:
Issue Dt:
08/16/2005
Application #:
10602720
Filing Dt:
06/25/2003
Publication #:
Pub Dt:
12/30/2004
Title:
MEMORY DEVICE AND METHODS OF CONTROLLING RESISTANCE VARIATION AND RESISTANCE PROFILE DRIFT
26
Patent #:
Issue Dt:
10/22/2013
Application #:
12232231
Filing Dt:
09/12/2008
Publication #:
Pub Dt:
03/18/2010
Title:
METHODS, SYSTEMS AND APPARATUSES FOR WHITE BALANCE CALIBRATION
Assignor
1
Exec Dt:
02/12/2010
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83706
Correspondence name and address
DICKSTEIN SHAPIRO LLP
1825 EYE STREET, NW
WASHINGTON, DC 20006

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