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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049602/0324   Pages: 20
Recorded: 06/26/2019
Attorney Dkt #:3771-GEN
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 56
1
Patent #:
6198113
Issue Dt:
03/06/2001
Application #:
09296858
Filing Dt:
04/22/1999
Title:
ELECTROSTATICALLY OPERATED TUNNELING TRANSISTOR
2
Patent #:
7615402
Issue Dt:
11/10/2009
Application #:
09612607
Filing Dt:
07/07/2000
Title:
ELECTROSTATICALLY OPERATED TUNNELING TRANSISTOR
3
Patent #:
7084423
Issue Dt:
08/01/2006
Application #:
10217758
Filing Dt:
08/12/2002
Publication #:
US20040026687
Pub Dt:
02/12/2004
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
4
Patent #:
6833556
Issue Dt:
12/21/2004
Application #:
10342576
Filing Dt:
01/14/2003
Publication #:
US20040026736
Pub Dt:
02/12/2004
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
5
Patent #:
7176483
Issue Dt:
02/13/2007
Application #:
10753504
Filing Dt:
01/07/2004
Publication #:
US20050093027
Pub Dt:
05/05/2005
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
6
Patent #:
7112478
Issue Dt:
09/26/2006
Application #:
10754966
Filing Dt:
01/09/2004
Publication #:
US20040142524
Pub Dt:
07/22/2004
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
7
Patent #:
6891234
Issue Dt:
05/10/2005
Application #:
10832576
Filing Dt:
04/26/2004
Title:
TRANSISTOR WITH WORKFUNCTION-INDUCED CHARGE LAYER
8
Patent #:
7382021
Issue Dt:
06/03/2008
Application #:
11010048
Filing Dt:
12/09/2004
Publication #:
US20050104137
Pub Dt:
05/19/2005
Title:
INSULATED GATE FIELD-EFFECT TRANSISTOR HAVING III-VI SOURCE/DRAIN LAYER(S)
9
Patent #:
7902029
Issue Dt:
03/08/2011
Application #:
11166286
Filing Dt:
06/23/2005
Publication #:
US20060084232
Pub Dt:
04/20/2006
Title:
PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR
10
Patent #:
7462860
Issue Dt:
12/09/2008
Application #:
11181217
Filing Dt:
07/13/2005
Publication #:
US20050247956
Pub Dt:
11/10/2005
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
11
Patent #:
7883980
Issue Dt:
02/08/2011
Application #:
11403185
Filing Dt:
04/11/2006
Publication #:
US20070026591
Pub Dt:
02/01/2007
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
12
Patent #:
7816240
Issue Dt:
10/19/2010
Application #:
11678397
Filing Dt:
02/23/2007
Publication #:
US20070224739
Pub Dt:
09/27/2007
Title:
METHOD FOR MAKING SEMICONDUCTOR INSULATED-GATE FIELD-EFFECT TRANSISTOR HAVING MULTILAYER DEPOSITED METAL SOURCE(S) AND/OR DRAIN(S)
13
Patent #:
7884003
Issue Dt:
02/08/2011
Application #:
12197996
Filing Dt:
08/25/2008
Publication #:
US20090104770
Pub Dt:
04/23/2009
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
14
Patent #:
8263466
Issue Dt:
09/11/2012
Application #:
12253835
Filing Dt:
10/17/2008
Publication #:
US20090104746
Pub Dt:
04/23/2009
Title:
CHANNEL STRAIN INDUCED BY STRAINED METAL IN FET SOURCE OR DRAIN
15
Patent #:
8450133
Issue Dt:
05/28/2013
Application #:
12404782
Filing Dt:
03/16/2009
Publication #:
US20100229929
Pub Dt:
09/16/2010
Title:
STRAINED-ENHANCED SILICON PHOTON-TO-ELECTRON CONVERSION DEVICES
16
Patent #:
8212336
Issue Dt:
07/03/2012
Application #:
12549227
Filing Dt:
08/27/2009
Publication #:
US20100065887
Pub Dt:
03/18/2010
Title:
FIELD EFFECT TRANSISTOR SOURCE OR DRAIN WITH A MULTI-FACET SURFACE
17
Patent #:
8395213
Issue Dt:
03/12/2013
Application #:
12869978
Filing Dt:
08/27/2010
Publication #:
US20120049280
Pub Dt:
03/01/2012
Title:
STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
18
Patent #:
8658523
Issue Dt:
02/25/2014
Application #:
12878930
Filing Dt:
09/09/2010
Publication #:
US20110008953
Pub Dt:
01/13/2011
Title:
METHOD FOR MAKING SEMICONDUCTOR INSULATED-GATE FIELD-EFFECT TRANSISTOR HAVING MULTILAYER DEPOSITED METAL SOURCE(S) AND/OR DRAIN(S)
19
Patent #:
8263467
Issue Dt:
09/11/2012
Application #:
13019789
Filing Dt:
02/02/2011
Publication #:
US20110124170
Pub Dt:
05/26/2011
Title:
PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR
20
Patent #:
8431469
Issue Dt:
04/30/2013
Application #:
13022522
Filing Dt:
02/07/2011
Publication #:
US20110169124
Pub Dt:
07/14/2011
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
21
Patent #:
8377767
Issue Dt:
02/19/2013
Application #:
13022559
Filing Dt:
02/07/2011
Publication #:
US20110210376
Pub Dt:
09/01/2011
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
22
Patent #:
8731017
Issue Dt:
05/20/2014
Application #:
13209186
Filing Dt:
08/12/2011
Publication #:
US20130039664
Pub Dt:
02/14/2013
Title:
TENSILE STRAINED SEMICONDUCTOR PHOTON EMISSION AND DETECTION DEVICES AND INTEGRATED PHOTONICS SYSTEM
23
Patent #:
9425277
Issue Dt:
08/23/2016
Application #:
13552556
Filing Dt:
07/18/2012
Publication #:
US20120280294
Pub Dt:
11/08/2012
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
24
Patent #:
8766336
Issue Dt:
07/01/2014
Application #:
13687907
Filing Dt:
11/28/2012
Publication #:
US20130119446
Pub Dt:
05/16/2013
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
25
Patent #:
8916437
Issue Dt:
12/23/2014
Application #:
13757597
Filing Dt:
02/01/2013
Publication #:
US20130140629
Pub Dt:
06/06/2013
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
26
Patent #:
9406798
Issue Dt:
08/02/2016
Application #:
13762677
Filing Dt:
02/08/2013
Publication #:
US20160240678
Pub Dt:
08/18/2016
Title:
STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
27
Patent #:
9029686
Issue Dt:
05/12/2015
Application #:
13870698
Filing Dt:
04/25/2013
Publication #:
US20130284269
Pub Dt:
10/31/2013
Title:
STRAIN-ENHANCED SILICON PHOTON-TO-ELECTRON CONVERSION DEVICES
28
Patent #:
9036672
Issue Dt:
05/19/2015
Application #:
14256758
Filing Dt:
04/18/2014
Publication #:
US20140369372
Pub Dt:
12/18/2014
Title:
Tensile Strained Semiconductor Photon Emission and Detection Devices and Integrated Photonics System
29
Patent #:
9583614
Issue Dt:
02/28/2017
Application #:
14298810
Filing Dt:
06/06/2014
Publication #:
US20140284666
Pub Dt:
09/25/2014
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
30
Patent #:
9362376
Issue Dt:
06/07/2016
Application #:
14360473
Filing Dt:
05/23/2014
Publication #:
US20140327142
Pub Dt:
11/06/2014
Title:
METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
31
Patent #:
9270083
Issue Dt:
02/23/2016
Application #:
14698759
Filing Dt:
04/28/2015
Publication #:
US20150249320
Pub Dt:
09/03/2015
Title:
Tensile Strained Semiconductor Photon Emission and Detection Devices and Integrated Photonics System
32
Patent #:
9209261
Issue Dt:
12/08/2015
Application #:
14743916
Filing Dt:
06/18/2015
Publication #:
US20150287800
Pub Dt:
10/08/2015
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
33
Patent #:
10008827
Issue Dt:
06/26/2018
Application #:
15000975
Filing Dt:
04/04/2016
Publication #:
US20160211649
Pub Dt:
07/21/2016
Title:
TENSILE STRAINED SEMICONDUCTOR PHOTON EMISSION AND DETECTION DEVICES AND INTEGRATED PHOTONICS SYSTEM
34
Patent #:
9484426
Issue Dt:
11/01/2016
Application #:
15043035
Filing Dt:
02/12/2016
Publication #:
US20160163813
Pub Dt:
06/09/2016
Title:
METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
35
Patent #:
9905691
Issue Dt:
02/27/2018
Application #:
15048877
Filing Dt:
02/19/2016
Publication #:
US20160172491
Pub Dt:
06/16/2016
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
36
Patent #:
9461167
Issue Dt:
10/04/2016
Application #:
15048893
Filing Dt:
02/19/2016
Publication #:
US20160172492
Pub Dt:
06/16/2016
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
37
Patent #:
9755038
Issue Dt:
09/05/2017
Application #:
15146562
Filing Dt:
05/04/2016
Publication #:
US20160247890
Pub Dt:
08/25/2016
Title:
METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
38
Patent #:
9620611
Issue Dt:
04/11/2017
Application #:
15186378
Filing Dt:
06/17/2016
Title:
MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR
39
Patent #:
9673327
Issue Dt:
06/06/2017
Application #:
15191369
Filing Dt:
06/23/2016
Publication #:
US20160308057
Pub Dt:
10/20/2016
Title:
STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
40
Patent #:
9812542
Issue Dt:
11/07/2017
Application #:
15251210
Filing Dt:
08/30/2016
Publication #:
US20160372564
Pub Dt:
12/22/2016
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
41
Patent #:
11043571
Issue Dt:
06/22/2021
Application #:
15418360
Filing Dt:
01/27/2017
Publication #:
US20170133476
Pub Dt:
05/11/2017
Title:
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
42
Patent #:
10147798
Issue Dt:
12/04/2018
Application #:
15451164
Filing Dt:
03/06/2017
Publication #:
US20180083115
Pub Dt:
03/22/2018
Title:
MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR
43
Patent #:
10084091
Issue Dt:
09/25/2018
Application #:
15594436
Filing Dt:
05/12/2017
Publication #:
US20170250283
Pub Dt:
08/31/2017
Title:
STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
44
Patent #:
NONE
Issue Dt:
Application #:
15655710
Filing Dt:
07/20/2017
Publication #:
US20170323973
Pub Dt:
11/09/2017
Title:
SOI WAFERS AND DEVICES WITH BURIED STRESSOR
45
Patent #:
10505005
Issue Dt:
12/10/2019
Application #:
15684707
Filing Dt:
08/23/2017
Publication #:
US20170373164
Pub Dt:
12/28/2017
Title:
METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
46
Patent #:
10388748
Issue Dt:
08/20/2019
Application #:
15728002
Filing Dt:
10/09/2017
Publication #:
US20180033862
Pub Dt:
02/01/2018
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
47
Patent #:
10193307
Issue Dt:
01/29/2019
Application #:
15800450
Filing Dt:
11/01/2017
Publication #:
US20180062352
Pub Dt:
03/01/2018
Title:
TENSILE STRAINED SEMICONDUCTOR PHOTON EMISSION AND DETECTION DEVICES AND INTEGRATED PHOTONICS SYSTEM
48
Patent #:
10170627
Issue Dt:
01/01/2019
Application #:
15816231
Filing Dt:
11/17/2017
Publication #:
US20180145184
Pub Dt:
05/24/2018
Title:
NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHT
49
Patent #:
NONE
Issue Dt:
Application #:
15877273
Filing Dt:
01/22/2018
Publication #:
US20180212056
Pub Dt:
07/26/2018
Title:
STRAINED SEMICONDUCTOR-ON-INSULATOR BY DEFORMATION OF BURIED INSULATOR INDUCED BY BURIED STRESSOR
50
Patent #:
10090395
Issue Dt:
10/02/2018
Application #:
15877837
Filing Dt:
01/23/2018
Publication #:
US20180166552
Pub Dt:
06/14/2018
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
51
Patent #:
10186592
Issue Dt:
01/22/2019
Application #:
15981594
Filing Dt:
05/16/2018
Publication #:
US20180269298
Pub Dt:
09/20/2018
Title:
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS
52
Patent #:
10580896
Issue Dt:
03/03/2020
Application #:
16105277
Filing Dt:
08/20/2018
Publication #:
US20190006518
Pub Dt:
01/03/2019
Title:
STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
53
Patent #:
10553695
Issue Dt:
02/04/2020
Application #:
16175637
Filing Dt:
10/30/2018
Publication #:
US20190067439
Pub Dt:
02/28/2019
Title:
MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR
54
Patent #:
10505047
Issue Dt:
12/10/2019
Application #:
16202507
Filing Dt:
11/28/2018
Publication #:
US20190109241
Pub Dt:
04/11/2019
Title:
NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHT
55
Patent #:
10727647
Issue Dt:
07/28/2020
Application #:
16213876
Filing Dt:
12/07/2018
Publication #:
US20190115726
Pub Dt:
04/18/2019
Title:
TENSILE STRAINED SEMICONDUCTOR PHOTON EMISSION AND DETECTION DEVICES AND INTEGRATED PHOTONICS SYSTEM
56
Patent #:
10833194
Issue Dt:
11/10/2020
Application #:
16283578
Filing Dt:
02/22/2019
Publication #:
US20200273991
Pub Dt:
08/27/2020
Title:
SOI WAFERS AND DEVICES WITH BURIED STRESSOR
Assignor
1
ACORN TECHNOLOGIES, INC.
Exec Dt:
05/30/2019
Assignee
1
ACORN SEMI, LLC
455 CAMBRIDGE AVE
PALO ALTO, CALIFORNIA 94306
Correspondence name and address
ASCENDA LAW GROUP
333 W. SAN CARLOS ST.
SUITE 200
SAN JOSE, CA 95110

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