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Reel/Frame:052557/0327   Pages: 13
Recorded: 05/04/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 158
Page 2 of 2
Pages: 1 2
1
Patent #:
NONE
Issue Dt:
Application #:
16354885
Filing Dt:
03/15/2019
Publication #:
US20190214309
Pub Dt:
07/11/2019
Title:
MONOLITHIC CO-INTEGRATION OF MOSFET AND JFET FOR NEUROMORPHIC/COGNITIVE CIRCUIT APPLICATIONS
2
Patent #:
NONE
Issue Dt:
Application #:
16358227
Filing Dt:
03/19/2019
Publication #:
US20190214253
Pub Dt:
07/11/2019
Title:
SiGe FINS FORMED ON A SUBSTRATE
3
Patent #:
NONE
Issue Dt:
Application #:
16358240
Filing Dt:
03/19/2019
Publication #:
US20190214254
Pub Dt:
07/11/2019
Title:
SiGe FINS FORMED ON A SUBSTRATE
4
Patent #:
NONE
Issue Dt:
Application #:
16360360
Filing Dt:
03/21/2019
Publication #:
US20190221484
Pub Dt:
07/18/2019
Title:
THREE-DIMENSIONAL STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR LOGIC GATE WITH BURIED POWER BUS
5
Patent #:
10985257
Issue Dt:
04/20/2021
Application #:
16362235
Filing Dt:
03/22/2019
Publication #:
US20190229200
Pub Dt:
07/25/2019
Title:
VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTOR WITH ASYMMETRIC CHANNEL PROFILE
6
Patent #:
NONE
Issue Dt:
Application #:
16369921
Filing Dt:
03/29/2019
Publication #:
US20190229204
Pub Dt:
07/25/2019
Title:
EFFECTIVE JUNCTION FORMATION IN VERTICAL TRANSISTOR STRUCTURES BY ENGINEERED BOTTOM SOURCE/DRAIN EPITAXY
7
Patent #:
10763343
Issue Dt:
09/01/2020
Application #:
16369990
Filing Dt:
03/29/2019
Publication #:
US20190229205
Pub Dt:
07/25/2019
Title:
EFFECTIVE JUNCTION FORMATION IN VERTICAL TRANSISTOR STRUCTURES BY ENGINEERED BOTTOM SOURCE/DRAIN EPITAXY
8
Patent #:
10790199
Issue Dt:
09/29/2020
Application #:
16371621
Filing Dt:
04/01/2019
Publication #:
US20190229020
Pub Dt:
07/25/2019
Title:
DUAL CHANNEL SILICON/SILICON GERMANIUM COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PERFORMANCE WITH INTERFACE ENGINEERING
9
Patent #:
NONE
Issue Dt:
Application #:
16388113
Filing Dt:
04/18/2019
Publication #:
US20190244926
Pub Dt:
08/08/2019
Title:
CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE
10
Patent #:
NONE
Issue Dt:
Application #:
16391826
Filing Dt:
04/23/2019
Publication #:
US20190252520
Pub Dt:
08/15/2019
Title:
LONG CHANNELS FOR TRANSISTORS
11
Patent #:
NONE
Issue Dt:
Application #:
16392018
Filing Dt:
04/23/2019
Publication #:
US20190252497
Pub Dt:
08/15/2019
Title:
LONG CHANNELS FOR TRANSISTORS
12
Patent #:
10832955
Issue Dt:
11/10/2020
Application #:
16392064
Filing Dt:
04/23/2019
Publication #:
US20190252263
Pub Dt:
08/15/2019
Title:
METHODS AND STRUCTURES FOR FORMING UNIFORM FINS WHEN USING HARDMASK PATTERNS
13
Patent #:
10622354
Issue Dt:
04/14/2020
Application #:
16398374
Filing Dt:
04/30/2019
Publication #:
US20190259752
Pub Dt:
08/22/2019
Title:
FINFETS WITH CONTROLLABLE AND ADJUSTABLE CHANNEL DOPING
14
Patent #:
NONE
Issue Dt:
Application #:
16401141
Filing Dt:
05/02/2019
Publication #:
US20190259754
Pub Dt:
08/22/2019
Title:
STRUCTURE AND METHOD TO SUPPRESS WORK FUNCTION EFFECT BY PATTERNING BOUNDARY PROXIMITY IN REPLACEMENT METAL GATE
15
Patent #:
NONE
Issue Dt:
Application #:
16402264
Filing Dt:
05/03/2019
Publication #:
US20190259852
Pub Dt:
08/22/2019
Title:
FINFET WITH REDUCED PARASITIC CAPACITANCE
16
Patent #:
10777482
Issue Dt:
09/15/2020
Application #:
16404949
Filing Dt:
05/07/2019
Publication #:
US20190259683
Pub Dt:
08/22/2019
Title:
MULTIPART LID FOR A SEMICONDUCTOR PACKAGE WITH MULTIPLE COMPONENTS
17
Patent #:
10790190
Issue Dt:
09/29/2020
Application #:
16405562
Filing Dt:
05/07/2019
Publication #:
US20190267285
Pub Dt:
08/29/2019
Title:
BACKSIDE CONTACT TO A FINAL SUBSTRATE
18
Patent #:
10607859
Issue Dt:
03/31/2020
Application #:
16405578
Filing Dt:
05/07/2019
Publication #:
US20190267253
Pub Dt:
08/29/2019
Title:
ADHESIVE-BONDED THERMAL INTERFACE STRUCTURES
19
Patent #:
NONE
Issue Dt:
Application #:
16405614
Filing Dt:
05/07/2019
Publication #:
US20190267254
Pub Dt:
08/29/2019
Title:
ADHESIVE-BONDED THERMAL INTERFACE STRUCTURES
20
Patent #:
NONE
Issue Dt:
Application #:
16406359
Filing Dt:
05/08/2019
Publication #:
US20190355625
Pub Dt:
11/21/2019
Title:
INVERSE TONE DIRECT PRINT EUV LITHOGRAPHY ENABLED BY SELECTIVE MATERIAL DEPOSITION
21
Patent #:
NONE
Issue Dt:
Application #:
16406443
Filing Dt:
05/08/2019
Publication #:
US20190267243
Pub Dt:
08/29/2019
Title:
LATERAL OXIDATION OF NFET AND PFET HIGH-K GATE STACKS
22
Patent #:
NONE
Issue Dt:
Application #:
16407892
Filing Dt:
05/09/2019
Publication #:
US20190267475
Pub Dt:
08/29/2019
Title:
SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
23
Patent #:
NONE
Issue Dt:
Application #:
16412526
Filing Dt:
05/15/2019
Publication #:
US20190267464
Pub Dt:
08/29/2019
Title:
EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS
24
Patent #:
10777647
Issue Dt:
09/15/2020
Application #:
16419287
Filing Dt:
05/22/2019
Publication #:
US20190273142
Pub Dt:
09/05/2019
Title:
FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE
25
Patent #:
10790284
Issue Dt:
09/29/2020
Application #:
16421673
Filing Dt:
05/24/2019
Publication #:
US20190279983
Pub Dt:
09/12/2019
Title:
SPACER FOR TRENCH EPITAXIAL STRUCTURES
26
Patent #:
10741559
Issue Dt:
08/11/2020
Application #:
16423727
Filing Dt:
05/28/2019
Publication #:
US20190296015
Pub Dt:
09/26/2019
Title:
SPACER FOR TRENCH EPITAXIAL STRUCTURES
27
Patent #:
10811410
Issue Dt:
10/20/2020
Application #:
16429210
Filing Dt:
06/03/2019
Publication #:
US20190287968
Pub Dt:
09/19/2019
Title:
SIMULTANEOUSLY FABRICATING A HIGH VOLTAGE TRANSISTOR AND A FINFET
28
Patent #:
NONE
Issue Dt:
Application #:
16430539
Filing Dt:
06/04/2019
Publication #:
US20190288012
Pub Dt:
09/19/2019
Title:
IMPLEMENTING A HYBRID FINFET DEVICE AND NANOWIRE DEVICE UTILIZING SELECTIVE SGOI
29
Patent #:
NONE
Issue Dt:
Application #:
16432377
Filing Dt:
06/05/2019
Publication #:
US20190326190
Pub Dt:
10/24/2019
Title:
WAFER STACKING FOR INTEGRATED CIRCUIT MANUFACTURING
30
Patent #:
10804278
Issue Dt:
10/13/2020
Application #:
16437383
Filing Dt:
06/11/2019
Publication #:
US20190312044
Pub Dt:
10/10/2019
Title:
HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS
31
Patent #:
10804366
Issue Dt:
10/13/2020
Application #:
16444295
Filing Dt:
06/18/2019
Publication #:
US20190305103
Pub Dt:
10/03/2019
Title:
INTEGRATED GATE DRIVER
32
Patent #:
NONE
Issue Dt:
Application #:
16444639
Filing Dt:
06/18/2019
Publication #:
US20190304968
Pub Dt:
10/03/2019
Title:
VERTICAL FIELD EFFECT TRANSISTOR (VFET) PROGRAMMABLE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INVERTER
33
Patent #:
NONE
Issue Dt:
Application #:
16502271
Filing Dt:
07/03/2019
Publication #:
US20190326397
Pub Dt:
10/24/2019
Title:
LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE
34
Patent #:
NONE
Issue Dt:
Application #:
16507683
Filing Dt:
07/10/2019
Publication #:
US20190341489
Pub Dt:
11/07/2019
Title:
FORMING A COMBINATION OF LONG CHANNEL DEVICES AND VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE
35
Patent #:
NONE
Issue Dt:
Application #:
16507843
Filing Dt:
07/10/2019
Publication #:
US20190334033
Pub Dt:
10/31/2019
Title:
FORMING A COMBINATION OF LONG CHANNEL DEVICES AND VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE
36
Patent #:
10573567
Issue Dt:
02/25/2020
Application #:
16515319
Filing Dt:
07/18/2019
Publication #:
US20190341318
Pub Dt:
11/07/2019
Title:
SACRIFICIAL CAP FOR FORMING SEMICONDUCTOR CONTACT
37
Patent #:
NONE
Issue Dt:
Application #:
16534045
Filing Dt:
08/07/2019
Publication #:
US20190362977
Pub Dt:
11/28/2019
Title:
SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER
38
Patent #:
NONE
Issue Dt:
Application #:
16543957
Filing Dt:
08/19/2019
Publication #:
US20190378929
Pub Dt:
12/12/2019
Title:
CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN
39
Patent #:
10943786
Issue Dt:
03/09/2021
Application #:
16547948
Filing Dt:
08/22/2019
Publication #:
US20190385854
Pub Dt:
12/19/2019
Title:
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CARBON NANOTUBE GATE
40
Patent #:
NONE
Issue Dt:
Application #:
16571690
Filing Dt:
09/16/2019
Publication #:
US20200013773
Pub Dt:
01/09/2020
Title:
FORMING ON-CHIP METAL-INSULATOR-SEMICONDUCTOR CAPACITOR
41
Patent #:
11227796
Issue Dt:
01/18/2022
Application #:
16575337
Filing Dt:
09/18/2019
Publication #:
US20200013671
Pub Dt:
01/09/2020
Title:
ENHANCEMENT OF ISO-VIA RELIABILITY
42
Patent #:
NONE
Issue Dt:
Application #:
16577443
Filing Dt:
09/20/2019
Publication #:
US20200020598
Pub Dt:
01/16/2020
Title:
SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
43
Patent #:
NONE
Issue Dt:
Application #:
16577571
Filing Dt:
09/20/2019
Publication #:
US20200013682
Pub Dt:
01/09/2020
Title:
SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
44
Patent #:
NONE
Issue Dt:
Application #:
16585314
Filing Dt:
09/27/2019
Publication #:
US20200027779
Pub Dt:
01/23/2020
Title:
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
45
Patent #:
10784137
Issue Dt:
09/22/2020
Application #:
16588082
Filing Dt:
09/30/2019
Publication #:
US20200027766
Pub Dt:
01/23/2020
Title:
PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE
46
Patent #:
10804166
Issue Dt:
10/13/2020
Application #:
16598517
Filing Dt:
10/10/2019
Publication #:
US20200043811
Pub Dt:
02/06/2020
Title:
POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
47
Patent #:
11177285
Issue Dt:
11/16/2021
Application #:
16661539
Filing Dt:
10/23/2019
Publication #:
US20200058677
Pub Dt:
02/20/2020
Title:
CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE
48
Patent #:
10937883
Issue Dt:
03/02/2021
Application #:
16662907
Filing Dt:
10/24/2019
Publication #:
US20200058753
Pub Dt:
02/20/2020
Title:
VERTICAL TRANSPORT FETS HAVING A GRADIENT THRESHOLD VOLTAGE
49
Patent #:
NONE
Issue Dt:
Application #:
16667132
Filing Dt:
10/29/2019
Publication #:
US20200075429
Pub Dt:
03/05/2020
Title:
LOCAL WIRING IN BETWEEN STACKED DEVICES
50
Patent #:
10916471
Issue Dt:
02/09/2021
Application #:
16669643
Filing Dt:
10/31/2019
Publication #:
US20200066583
Pub Dt:
02/27/2020
Title:
DUAL SILICIDE LINER FLOW FOR ENABLING LOW CONTACT RESISTANCE
51
Patent #:
10804107
Issue Dt:
10/13/2020
Application #:
16671218
Filing Dt:
11/01/2019
Publication #:
US20200066531
Pub Dt:
02/27/2020
Title:
WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING
52
Patent #:
NONE
Issue Dt:
Application #:
16671637
Filing Dt:
11/01/2019
Publication #:
US20200066724
Pub Dt:
02/27/2020
Title:
PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS
53
Patent #:
10957536
Issue Dt:
03/23/2021
Application #:
16671686
Filing Dt:
11/01/2019
Publication #:
US20200066519
Pub Dt:
02/27/2020
Title:
REMOVAL OF TRILAYER RESIST WITHOUT DAMAGE TO UNDERLYING STRUCTURE
54
Patent #:
10833156
Issue Dt:
11/10/2020
Application #:
16674025
Filing Dt:
11/05/2019
Publication #:
US20200075714
Pub Dt:
03/05/2020
Title:
SELF-FORMING SPACERS USING OXIDATION
55
Patent #:
NONE
Issue Dt:
Application #:
16682537
Filing Dt:
11/13/2019
Publication #:
US20200083342
Pub Dt:
03/12/2020
Title:
INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
56
Patent #:
NONE
Issue Dt:
Application #:
16682687
Filing Dt:
11/13/2019
Publication #:
US20200083106
Pub Dt:
03/12/2020
Title:
FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN
57
Patent #:
11088026
Issue Dt:
08/10/2021
Application #:
16717564
Filing Dt:
12/17/2019
Publication #:
US20200126862
Pub Dt:
04/23/2020
Title:
WIMPY DEVICE BY SELECTIVE LASER ANNEALING
58
Patent #:
10978454
Issue Dt:
04/13/2021
Application #:
16776686
Filing Dt:
01/30/2020
Publication #:
US20200168608
Pub Dt:
05/28/2020
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
03/06/2020
Assignee
1
ELPIS TECHNOLOGIES INC.
1891 ROBERSTON ROAD
SUITE 100
OTTAWA, CANADA K2H 5B7
Correspondence name and address
ELPIS TECHNOLOGIES INC.
1891 ROBERSTON ROAD
SUITE 100
OTTAWA, K2H 5B7 CANADA

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