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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10189748
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Filing Dt:
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07/08/2002
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Publication #:
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Pub Dt:
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01/08/2004
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Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10210771
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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METHOD AND APPARATUS FOR NON-LINEAR TERMINATION OF A TRANSMISSION LINE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10215279
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Filing Dt:
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08/12/2002
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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INTEGRATED CIRCUIT AND LAMINATED LEADFRAME PACKAGE
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10217497
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Filing Dt:
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08/13/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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CIRCUIT AND METHOD FOR A PROGRAMMABLE REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10217661
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Filing Dt:
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08/13/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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PROGRAMMABLE DATA DEVICE AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10219167
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Filing Dt:
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08/16/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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METHOD OF MAKING A VERTICAL GATE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10219190
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Filing Dt:
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08/16/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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SELF-ALIGNED VERTICAL GATE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10228374
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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METHOD OF FORMING A POWER DEVICE AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10228728
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Filing Dt:
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08/26/2002
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Title:
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SILICON SUB-MOUNT CAPABLE OF SINGLE WIRE BONDING AND OF PROVIDING ESD PROTECTION FOR LIGHT EMITTING DIODE DEVICES
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10237123
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Filing Dt:
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09/09/2002
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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STRUCTURE AND METHOD OF DIRECT CHIP ATTACH
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10238078
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Filing Dt:
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09/09/2002
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Title:
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REGULATOR FOR DDR DRAM TERMINATION VOLTAGE
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10243749
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Filing Dt:
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09/13/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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INTEGRATED OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION CIRCUIT
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10262437
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Filing Dt:
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09/30/2002
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Title:
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ABSOLUTE VALUE AMPLITUDE BASEBAND DETECTOR
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10270401
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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SEMICONDUCTOR DEVICE AND LAMINATED LEADFRAME PACKAGE
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10270413
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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METHOD OF FORMING AN AUDIO AMPLIFIER VOLTAGE REFERENCE AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10270419
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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METHOD OF FORMING A LOW RESISTANCE SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10277454
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Filing Dt:
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10/22/2002
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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METHOD AND SYSTEM FOR REAL-TIME SPEECH RECOGNITION
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10277598
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Filing Dt:
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10/22/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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METHOD AND SYSTEM FOR REAL TIME AUDIO SYNTHESIS
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10287831
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Filing Dt:
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11/05/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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INTEGRATED INRUSH CURRENT LIMITER CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10291015
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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INTEGRATED INRUSH CURRENT LIMITER CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10303168
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Filing Dt:
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11/25/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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INTEGRATED CIRCUIT WITH VERTICAL PNP TRANSISTOR AND METHOD
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10305773
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Filing Dt:
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11/27/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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SEMICONDUCTOR DEVICE WITH PARALLEL PLATE TRENCH CAPACITOR AND METHOD
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10307590
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Filing Dt:
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12/02/2002
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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STRUCTURE AND METHOD OF MAKING A HIGH PERFORMANCE SEMICONDUCTOR DEVICE HAVING A NARROW DOPING PROFILE
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10313225
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Filing Dt:
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12/09/2002
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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POWER SWITCHING TRANSISTOR WITH LOW DRAIN TO GATE CAPACITANCE
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10340492
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Filing Dt:
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01/10/2003
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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LOW DROPOUT VOLTAGE REGULATOR WITH NON-MILLER FREQUENCY COMPENSATION
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10348093
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Filing Dt:
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01/21/2003
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Publication #:
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Pub Dt:
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07/22/2004
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Title:
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USE OF IRREGULARLY SHAPED CONDUCTIVE FILLER FEATURES TO IMPROVE PLANARIZATION OF THE CONDUCTIVE LAYER WHILE REDUCING PARASITIC CAPACITANCE INTRODUCED BY THE FILLER FEATURES
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10359319
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Filing Dt:
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02/07/2003
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Title:
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METHOD OF FORMING A BI-DIRECTIONAL SYNCHRONIZATION CONTROLLER
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10369230
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Filing Dt:
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02/20/2003
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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METHOD OF FORMING A VARIABLE PROPAGATION DELAY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10369471
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Filing Dt:
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02/21/2003
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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METHOD OF FORMING AN RF DETECTOR AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10373911
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Filing Dt:
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02/24/2003
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Title:
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METHODS FOR SIDEWALL PROTECTION OF METAL INTERCONNECT FOR UNLANDED VIAS USING PHYSICAL VAPOR DEPOSITION
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10373912
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Filing Dt:
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02/24/2003
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Title:
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LOW VOLTAGE ENHANCED OUTPUT IMPEDANCE CURRENT MIRROR
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10374099
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
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09/02/2004
| | | | |
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Title:
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POWER MANAGEMENT METHOD AND STRUCTURE
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10374630
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
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10/30/2003
| | | | |
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Title:
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STRUCTURE AND METHOD OF FORMING A MULTIPLE LEADFRAME SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10384094
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Filing Dt:
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03/07/2003
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Title:
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STIMULATED QUICK START OSCILLATOR
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10387824
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Filing Dt:
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03/12/2003
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Title:
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DIFFERENTIAL NOR MEMORY CELL HAVING TWO FLOATING GATE TRANSISTORS
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10389281
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Filing Dt:
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03/13/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
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Title:
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METHOD AND APPARATUS FOR NON-LINEAR TERMINATION OF A TRANSMISSION LINE
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10393333
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Filing Dt:
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03/20/2003
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Title:
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STABLE FLOATING GATE VOLTAGE REFERENCE USING INTERCONNECTED CURRENT-TO-VOLTAGE AND VOLTAGE-TO-CURRENT CONVERTERS
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10401082
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Filing Dt:
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03/27/2003
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Title:
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SWITCHED CAPACITOR VOLTAGE REFERENCE CIRCUITS USING TRANSCONDUCTANCE CIRCUIT TO GENERATE REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10406526
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Filing Dt:
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04/03/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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STATIC RANDOM ACCESS MEMORY (SRAM) WITHOUT PRECHARGE CIRCUITRY
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10422137
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Filing Dt:
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04/24/2003
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Publication #:
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Pub Dt:
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10/28/2004
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Title:
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DISTRIBUTED MEMORY AND LOGIC CIRCUITS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10426225
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Filing Dt:
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04/29/2003
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Title:
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UP-CONVERSION OF A DOWN-CONVERTED BASEBAND SIGNAL IN A DIRECT CONVERSION ARCHITECTURE WITHOUT THE BASEBAND SIGNAL PASSING THROUGH ACTIVE ELEMENTS
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10426383
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Filing Dt:
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04/29/2003
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Title:
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DIRECT CONVERSION RECEIVER FOR AMPLITUDE MODULATED SIGNALS USING LINEAR/LOG FILTERING
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10430455
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Filing Dt:
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05/06/2003
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Publication #:
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Pub Dt:
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11/11/2004
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Title:
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ADAPTIVE DIVERSITY RECEIVER ARCHITECTURE
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10430656
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Filing Dt:
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05/06/2003
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Title:
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DIRECT CONVERSION RECEIVER WITH DIRECT CURRENT OFFSET CORRECTION CIRCUITRY
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10432537
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Filing Dt:
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05/22/2003
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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CONTROLLED FREQUENCY POWER FACTOR CORRECTION CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10442618
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Filing Dt:
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05/20/2003
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Title:
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BI-DIRECTIONAL CURRENT MEASUREMENT CIRCUIT THAT USES A TRANSCONDUCTANCE AMPLIFIER TO GENERATE A COPY CURRENT
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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10442630
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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MULTI-FAULT PROTECTED HIGH SIDE SWITCH WITH CURRENT SENSE
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10446306
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Filing Dt:
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05/28/2003
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Title:
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SYMMETRIC AND COMPLEMENTARY DIFFERENTIAL AMPLIFIER
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10454870
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Filing Dt:
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06/06/2003
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
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Title:
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SEMICONDUCTOR POWER DEVICE HAVING A DIAMOND SHAPED METAL INTERCONNECT SCHEME
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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10463979
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Filing Dt:
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06/17/2003
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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LED DRIVER WITH INTEGRATED BIAS AND DIMMING CONTROL STORAGE
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10464100
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Filing Dt:
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06/19/2003
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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METHOD OF FORMING A REFERENCE VOLTAGE GENERATOR AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10464971
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Filing Dt:
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06/20/2003
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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METHOD OF FORMING A VERTICAL POWER SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10498703
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Filing Dt:
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06/11/2004
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A HIGH CONTRAST IDENTIFICATION MARK
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10600125
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Filing Dt:
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06/20/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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NON-VOLATILE MEMORY INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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10602195
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Filing Dt:
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06/24/2003
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Title:
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DELAY LOCKED LOOP WITH FIXED ANGLE DE-SKEW, QUICK START AND LOW JITTER
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Patent #:
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Issue Dt:
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12/05/2006
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Application #:
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10603257
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Filing Dt:
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06/26/2003
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Publication #:
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Pub Dt:
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12/30/2004
| | | | |
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Title:
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METHOD FOR MAKING A DIRECT CHIP ATTACH DEVICE AND STRUCTURE
|
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10611714
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Filing Dt:
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07/01/2003
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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DOUBLE-SIDED EXTENDED DRAIN FIELD EFFECT TRANSISTOR, AND INTEGRATED OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION CIRCUIT THAT USES THE SAME
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10615171
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Filing Dt:
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07/09/2003
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Publication #:
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Pub Dt:
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01/13/2005
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Title:
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SYMMETRICAL HIGH FREQUENCY SCR STRUCTURE
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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10615440
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Filing Dt:
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07/07/2003
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Title:
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DUAL DIFFERENTIAL-INPUT AMPLIFIER HAVING WIDE INPUT RANGE
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10620259
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Filing Dt:
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07/15/2003
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10623390
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Filing Dt:
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07/18/2003
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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DC/DC CONVERTER WITH DEPLETION MODE COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR SWITCHING DEVICE
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10623392
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Filing Dt:
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07/18/2003
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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METHOD OF MAKING A VERTICAL COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10623870
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Filing Dt:
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07/18/2003
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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SEMICONDUCTOR ASSEMBLY METHOD AND EQUIPMENT THEREFOR
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10626256
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Filing Dt:
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07/23/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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SYSTEM AND METHOD FOR PROGRAMMING NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10637405
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Filing Dt:
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08/08/2003
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Title:
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CELL STRUCTURE FOR BIPOLAR INTEGRATED CIRCUITS AND METHOD
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Patent #:
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Issue Dt:
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06/21/2005
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Application #:
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10637840
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Filing Dt:
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08/08/2003
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Title:
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DIGITALLY CONTROLLED IMPEDANCE DRIVER MATCHING FOR WIDE VOLTAGE SWINGS AT INPUT/OUTPUT NODE AND HAVING PROGRAMMABLE STEP SIZE
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10638181
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Filing Dt:
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08/11/2003
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Publication #:
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Pub Dt:
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02/17/2005
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Title:
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METHOD OF FORMING A LEADFRAME FOR A SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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08/30/2005
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Application #:
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10638227
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Filing Dt:
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08/11/2003
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Publication #:
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Pub Dt:
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02/17/2005
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Title:
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METHOD OF FORMING A HIGH EFFICIENCY POWER CONTROLLER
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10642539
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Filing Dt:
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08/18/2003
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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METHOD OF FORMING A VARIABLE FREQUENCY OSCILLATOR AND STRUCTURE THEREFOR
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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10642847
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Filing Dt:
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08/18/2003
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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METHOD AND SYSTEM FOR PROCESSING SUBBAND SIGNALS USING ADAPTIVE FILTERS
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10656982
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Filing Dt:
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09/05/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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PROGRAMMABLE ANALOG BIAS CIRCUITS USING FLOATING GATE CMOS TECHNOLOGY
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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10660222
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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DIGITAL POTENTIOMETER INCLUDING PLURAL BULK IMPEDANCE DEVICES
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|
|
|
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10660232
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
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DIGITAL POTENTIOMETER INCLUDING AT LEAST ONE BULK IMPEDANCE DEVICE
|
|
|
|
|
Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10662062
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Filing Dt:
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09/15/2003
|
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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METHOD AND CIRCUIT FOR OPTIMIZING POWER EFFICIENCY IN A DC-DC CONVERTER
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|
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10670978
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Filing Dt:
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09/26/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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DIFFERENTIAL TRANSISTOR AND METHOD THEREFOR
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|
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10678769
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Filing Dt:
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10/06/2003
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Publication #:
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Pub Dt:
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04/07/2005
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Title:
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POWER SWITCH STRUCTURE WITH LOW RDSON AND LOW CURRENT LIMIT AND METHOD
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|
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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10681813
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Filing Dt:
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10/07/2003
|
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Publication #:
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Pub Dt:
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04/07/2005
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Title:
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LINEAR REGULATOR WITH OVERCURRENT PROTECTION
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|
|
|
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10685091
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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04/14/2005
| | | | |
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Title:
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POWER SYSTEM INHIBIT METHOD AND DEVICE AND STRUCTURE THEREFOR
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|
|
|
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10685094
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Filing Dt:
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10/14/2003
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|
Publication #:
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Pub Dt:
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04/14/2005
| | | | |
|
Title:
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POWER CONTROL SYSTEM STARTUP METHOD AND CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
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02/28/2006
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Application #:
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10723948
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Filing Dt:
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11/26/2003
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|
Publication #:
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Pub Dt:
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06/10/2004
| | | | |
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Title:
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DIGITAL POTENTIOMETER INCLUDING OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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01/03/2006
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Application #:
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10729292
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Filing Dt:
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12/08/2003
|
|
Publication #:
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Pub Dt:
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06/16/2005
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Title:
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LATERAL FET STRUCTURE WITH IMPROVED BLOCKING VOLTAGE AND ON RESISTANCE PERFORMANCE AND METHOD
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|
|
|
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10729892
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Filing Dt:
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12/08/2003
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Publication #:
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Pub Dt:
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06/16/2005
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Title:
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METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND LEADFRAME THEREFOR
|
|
|
|
|
Patent #:
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|
Issue Dt:
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03/13/2007
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Application #:
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10741330
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGE AND REDUCED ON RESISTANCE AND METHOD
|
|
|
|
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Patent #:
|
|
Issue Dt:
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08/29/2006
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Application #:
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10750267
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Filing Dt:
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01/02/2004
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
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Title:
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HIGH ENERGY ESD STRUCTURE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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05/30/2006
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Application #:
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10752772
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Filing Dt:
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01/08/2004
|
|
Publication #:
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Pub Dt:
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07/14/2005
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Title:
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METHOD OF FORMING AN EPROM CELL AND STRUCTURE THEREFOR
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|
|
|
|
Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10762650
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Filing Dt:
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01/21/2004
|
|
Publication #:
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Pub Dt:
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07/21/2005
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Title:
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SWITCHED NOISE FILTER CIRCUIT FOR A DC-DC CONVERTER
|
|
|
|
|
Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10770233
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Filing Dt:
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02/02/2004
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Title:
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TEMPERATURE STABLE VOLTAGE REFERENCE CIRCUIT USING A METAL-SILICON SCHOTTKY DIODE FOR LOW VOLTAGE CIRCUIT APPLICATIONS
|
|
|
|
|
Patent #:
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|
Issue Dt:
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08/08/2006
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Application #:
|
10773853
|
Filing Dt:
|
02/09/2004
|
|
Publication #:
|
|
Pub Dt:
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08/11/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING REDUCED CAPACITANCE TO SUBSTRATE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10797537
|
Filing Dt:
|
03/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
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HIGH VOLTAGE LATERAL FET STRUCTURE WITH IMPROVED ON RESISTANCE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10805405
|
Filing Dt:
|
03/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
METHOD OF FORMING A TRANSISTOR DRIVER AND STRUCTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10810864
|
Filing Dt:
|
03/29/2004
|
|
Publication #:
|
|
Pub Dt:
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09/29/2005
| | | | |
|
Title:
|
LOW AUDIBLE NOISE POWER SUPPLY CONTROLLER AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10811050
|
Filing Dt:
|
03/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
|
Title:
|
METHOD OF FORMING A FLOATING CHARGE PUMP AND STRUCTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10813501
|
Filing Dt:
|
03/31/2004
|
|
Publication #:
|
|
Pub Dt:
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10/06/2005
| | | | |
|
Title:
|
METHOD OF FORMING A SELF-GATED TRANSISTOR AND STRUCTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10825720
|
Filing Dt:
|
04/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR STARTUP BOOTSTRAP FOR INTERNAL REGULATORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10830171
|
Filing Dt:
|
04/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
SWITCH CONTROLLER FOR A POWER CONTROL SYSTEM AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
10831017
|
Filing Dt:
|
04/22/2004
|
|
Title:
|
SPREAD SPECTRUM CONTROLLABLE DELAY CLOCK BUFFER WITH ZERO CYCLE SLIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10840486
|
Filing Dt:
|
05/06/2004
|
|
Publication #:
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|
Pub Dt:
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10/21/2004
| | | | |
|
Title:
|
SEMICONDUCTOR BIDIRECTIONAL SWITCHING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10841330
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
|
|
Pub Dt:
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11/10/2005
| | | | |
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Title:
|
SECONDARY SIDE POWER SUPPLY CONTROLLER AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10841670
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHOD OF FORMING A SUPER-JUNCTION SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10842393
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
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|
Pub Dt:
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10/21/2004
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Title:
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SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING
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