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Reel/Frame:025420/0349   Pages: 13
Recorded: 11/24/2010
Attorney Dkt #:SAMSUNG SETTLEMENT
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 15
1
Patent #:
Issue Dt:
08/12/1997
Application #:
07686392
Filing Dt:
04/17/1991
Title:
METHOD FOR FABRICATING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING STORAGE CELL ARRAY AND PERIPHERAL CIRCUIT, AND A STRUCTURE THEREOF
2
Patent #:
Issue Dt:
06/07/1994
Application #:
07726180
Filing Dt:
07/05/1991
Title:
ARRANGEMENT OF WORD LINE DRIVER STAGE FOR SEMICONDUCTOR MEMORY DEVICE
3
Patent #:
Issue Dt:
09/05/1995
Application #:
08268948
Filing Dt:
06/30/1994
Title:
ISOLATION METHOD OF SEMICONDUCTOR DEVICE
4
Patent #:
Issue Dt:
05/02/2000
Application #:
08614766
Filing Dt:
03/13/1996
Title:
METHOD FOR DESIGNING CELL ARRAY LAYOUT OF NON-VOLATILE MEMORY DEVICE
5
Patent #:
Issue Dt:
06/01/1999
Application #:
08643885
Filing Dt:
05/07/1996
Title:
METHOD OF FORMING A POLYCIDE GATE OF A SEMICONDUCTOR DEVICE
6
Patent #:
Issue Dt:
09/15/1998
Application #:
08694541
Filing Dt:
08/09/1996
Title:
INTEGRATED CIRCUITS, AND METHODS OF FABRICATING SAME, WHICH TAKE INTO ACCOUNT CAPACITIVE LOADING BY THE INTEGRATED CIRCUIT POTTING MATERIAL
7
Patent #:
Issue Dt:
06/09/1998
Application #:
08709249
Filing Dt:
09/10/1996
Title:
METHOD OF FABRICATING MICROELECTRONIC CAPACITORS HAVING TANTALUM PENTOXIDE DIELECTRICS AND OXYGEN BARRIERS
8
Patent #:
Issue Dt:
09/08/1998
Application #:
08744436
Filing Dt:
11/08/1996
Title:
COMBINED FIELD/TRENCH ISOLATION REGION FABRICATION METHODS
9
Patent #:
Issue Dt:
01/12/1999
Application #:
08843799
Filing Dt:
04/21/1997
Title:
MICROELECTRONIC CAPACITORS HAVING TANTALUM PENTOXIDE DIELECTRICS AND OXGEN BARRIERS
10
Patent #:
Issue Dt:
02/22/2000
Application #:
09052249
Filing Dt:
03/31/1998
Title:
METHODS OF DESIGNING AND FABRICATING INTERGRATED CIRCUITS WHICH TAKE INTO ACCOUNT CAPACITIVE LOADING BY THE INTERGRATED CIRCUIT POTTING MATERIAL
11
Patent #:
Issue Dt:
06/06/2000
Application #:
09209649
Filing Dt:
12/10/1998
Title:
CONTACT STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE FOR REDUCING CONTACT RELATED DEFECT AND CONTACT RESISTANCE AND METHOD FOR FORMING THE SAME
12
Patent #:
Issue Dt:
08/27/2002
Application #:
09359438
Filing Dt:
07/22/1999
Title:
DEVICES FOR CONTROLLING TEMPERATURE INDICATIONS IN INTEGRATED CIRCUITS USING ADJUSTABLE THRESHOLD TEMPERATURES
13
Patent #:
Issue Dt:
08/17/2004
Application #:
10035247
Filing Dt:
01/04/2002
Publication #:
Pub Dt:
09/12/2002
Title:
SEMICONDUCTOR DEVICE HAVING NO CRACKS IN ONE OR MORE LAYERS UNDERLYING A METAL LINE LAYER AND METHOD OF MANUFACTURING THE SAME
14
Patent #:
Issue Dt:
08/01/2006
Application #:
10818692
Filing Dt:
04/06/2004
Publication #:
Pub Dt:
01/20/2005
Title:
CIRCUIT AND METHOD OF GENERATING A BOOSTED VOLTAGE
15
Patent #:
Issue Dt:
06/19/2007
Application #:
10885971
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
12/09/2004
Title:
SEMICONDUCTOR DEVICE HAVING NO CRACKS IN ONE OR MORE LAYERS UNDERLYING A METAL LINE LAYER AND METHOD OF MANUFACTURING THE SAME
Assignor
1
Exec Dt:
10/26/2010
Assignee
1
11 HINES ROAD
SUITE 203
OTTAWA, CANADA K2K 2X1
Correspondence name and address
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD
SUITE 203
OTTAWA, K2K 2X1 CANADA

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