Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 036148/0359 | |
| Pages: | 10 |
| | Recorded: | 07/21/2015 | | |
| Attorney Dkt #: | IOSEP009CIP1C1+C2 |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 035901 FRAME 0638. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE NAME SHOULD BE "IO SEMICONDUCTOR INCORPORATED". |
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Total properties:
2
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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13762257
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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TRAP RICH LAYER WITH THROUGH-SILICON-VIAS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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01/31/2017
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Application #:
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14043764
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Filing Dt:
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10/01/2013
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Publication #:
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Pub Dt:
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01/30/2014
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Title:
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TRAP RICH LAYER WITH THROUGH-SILICON-VIAS IN SEMICONDUCTOR DEVICES
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Assignee
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| 4350 EXECUTIVE DRIVE, SUITE 200 |
| SAN DIEGO, CALIFORNIA 92121 |
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Correspondence name and address
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ERIC SCHEUERLEIN
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THE MUELLER LAW OFFICE
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12707 HIGH BLUFF DR STE 200
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SAN DIEGO, CA 92130
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