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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038320/0364   Pages: 8
Recorded: 03/31/2016
Attorney Dkt #:063787-464932
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 52
1
Patent #:
7072825
Issue Dt:
07/04/2006
Application #:
10463057
Filing Dt:
06/16/2003
Publication #:
US20040254779
Pub Dt:
12/16/2004
Title:
HIERARCHICAL, NETWORK-BASED EMULATION SYSTEM
2
Patent #:
7117143
Issue Dt:
10/03/2006
Application #:
10735341
Filing Dt:
12/11/2003
Publication #:
US20050131670
Pub Dt:
06/16/2005
Title:
CLOCK DISTRIBUTION IN A CIRCUIT EMULATOR
3
Patent #:
7120571
Issue Dt:
10/10/2006
Application #:
10735342
Filing Dt:
12/11/2003
Publication #:
US20040254906
Pub Dt:
12/16/2004
Title:
RESOURCE BOARD FOR EMULATION SYSTEM
4
Patent #:
7366652
Issue Dt:
04/29/2008
Application #:
11230999
Filing Dt:
09/19/2005
Publication #:
US20060015313
Pub Dt:
01/19/2006
Title:
METHOD OF PROGRAMMING A CO-VERIFICATION SYSTEM
5
Patent #:
7703054
Issue Dt:
04/20/2010
Application #:
11697869
Filing Dt:
04/09/2007
Publication #:
US20080250378
Pub Dt:
10/09/2008
Title:
CIRCUIT EMULATION AND DEBUGGING METHOD
6
Patent #:
7895027
Issue Dt:
02/22/2011
Application #:
12015779
Filing Dt:
01/17/2008
Publication #:
US20090187394
Pub Dt:
07/23/2009
Title:
HDL RE-SIMULATION FROM CHECKPOINTS
7
Patent #:
7970597
Issue Dt:
06/28/2011
Application #:
12120895
Filing Dt:
05/15/2008
Publication #:
US20090287468
Pub Dt:
11/19/2009
Title:
EVENT-DRIVEN EMULATION SYSTEM
8
Patent #:
8255853
Issue Dt:
08/28/2012
Application #:
12756990
Filing Dt:
04/08/2010
Publication #:
US20110251836
Pub Dt:
10/13/2011
Title:
CIRCUIT EMULATION SYSTEMS AND METHODS
9
Patent #:
8336001
Issue Dt:
12/18/2012
Application #:
12913674
Filing Dt:
10/27/2010
Publication #:
US20110107278
Pub Dt:
05/05/2011
Title:
METHOD FOR IMPROVING YIELD RATE USING REDUNDANT WIRE INSERTION
10
Patent #:
8407647
Issue Dt:
03/26/2013
Application #:
12970888
Filing Dt:
12/16/2010
Publication #:
US20110154282
Pub Dt:
06/23/2011
Title:
SYSTEMS AND METHODS FOR DESIGNING AND MAKING INTEGRATED CIRCUITS WITH CONSIDERATION OF WIRING DEMAND RATIO
11
Patent #:
8281280
Issue Dt:
10/02/2012
Application #:
13025809
Filing Dt:
02/11/2011
Publication #:
US20110202894
Pub Dt:
08/18/2011
Title:
METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM
12
Patent #:
9081924
Issue Dt:
07/14/2015
Application #:
13047007
Filing Dt:
03/14/2011
Publication #:
US20110238397
Pub Dt:
09/29/2011
Title:
METHOD AND APPARATUS FOR TRANSACTION RECORDING AND VISUALIZATION
13
Patent #:
8261223
Issue Dt:
09/04/2012
Application #:
13093814
Filing Dt:
04/25/2011
Publication #:
US20110202897
Pub Dt:
08/18/2011
Title:
HIERARCHY-BASED ANALYTICAL PLACEMENT METHOD CAPABLE OF MACRO ROTATION WITHIN AN INTEGRATED CIRCUIT
14
Patent #:
8522176
Issue Dt:
08/27/2013
Application #:
13103099
Filing Dt:
05/08/2011
Publication #:
US20110283247
Pub Dt:
11/17/2011
Title:
METHOD OF RECORDING AND REPLAYING CALL FRAMES FOR THE TESTBENCH
15
Patent #:
8707226
Issue Dt:
04/22/2014
Application #:
13154068
Filing Dt:
06/06/2011
Publication #:
US20110307854
Pub Dt:
12/15/2011
Title:
MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN
16
Patent #:
8365132
Issue Dt:
01/29/2013
Application #:
13158471
Filing Dt:
06/13/2011
Publication #:
US20110320991
Pub Dt:
12/29/2011
Title:
HIERARCHIAL POWER MAP FOR LOW POWER DESIGN
17
Patent #:
8789008
Issue Dt:
07/22/2014
Application #:
13189014
Filing Dt:
07/22/2011
Publication #:
US20120066659
Pub Dt:
03/15/2012
Title:
METHODS FOR GENERATING DEVICE LAYOUTS BY COMBINING AN AUTOMATED DEVICE LAYOUT GENERATOR WITH A SCRIPT
18
Patent #:
9053264
Issue Dt:
06/09/2015
Application #:
13269085
Filing Dt:
10/07/2011
Publication #:
US20120239370
Pub Dt:
09/20/2012
Title:
WHAT-IF SIMULATION METHODS AND SYSTEMS
19
Patent #:
NONE
Issue Dt:
Application #:
13277229
Filing Dt:
10/20/2011
Publication #:
US20120180014
Pub Dt:
07/12/2012
Title:
METHOD OF CONTEXT-SENSITIVE, TRANS-REFLEXIVE INCREMENTAL DESIGN RULE CHECKING AND ITS APPLICATIONS
20
Patent #:
8683417
Issue Dt:
03/25/2014
Application #:
13289963
Filing Dt:
11/04/2011
Publication #:
US20120137264
Pub Dt:
05/31/2012
Title:
MULTIPLE LEVEL SPINE ROUTING
21
Patent #:
8959473
Issue Dt:
02/17/2015
Application #:
13289965
Filing Dt:
11/04/2011
Publication #:
US20120137265
Pub Dt:
05/31/2012
Title:
MULTIPLE LEVEL SPINE ROUTING
22
Patent #:
8296708
Issue Dt:
10/23/2012
Application #:
13349584
Filing Dt:
01/13/2012
Title:
METHOD OF CONSTRAINT-HIERARCHY-DRIVEN IC PLACEMENT
23
Patent #:
8671383
Issue Dt:
03/11/2014
Application #:
13443523
Filing Dt:
04/10/2012
Publication #:
US20130047134
Pub Dt:
02/21/2013
Title:
VIEWING AND DEBUGGING HDL DESIGNS HAVING SYSTEMVERILOG INTERFACE CONSTRUCTS
24
Patent #:
10152482
Issue Dt:
12/11/2018
Application #:
13449334
Filing Dt:
04/18/2012
Publication #:
US20130091098
Pub Dt:
04/11/2013
Title:
METHOD OF SPEEDING UP ACCESS TO DESIGN DATABASES HAVING LARGE NUMBERS OF DESIGN UNITS
25
Patent #:
8607182
Issue Dt:
12/10/2013
Application #:
13476027
Filing Dt:
05/21/2012
Publication #:
US20120304139
Pub Dt:
11/29/2012
Title:
METHOD OF FAST ANALOG LAYOUT MIGRATION
26
Patent #:
8739089
Issue Dt:
05/27/2014
Application #:
13596069
Filing Dt:
08/28/2012
Publication #:
US20130055177
Pub Dt:
02/28/2013
Title:
SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS
27
Patent #:
8732650
Issue Dt:
05/20/2014
Application #:
13597997
Filing Dt:
08/29/2012
Publication #:
US20130035925
Pub Dt:
02/07/2013
Title:
METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM
28
Patent #:
8893069
Issue Dt:
11/18/2014
Application #:
13646664
Filing Dt:
10/06/2012
Publication #:
US20130091481
Pub Dt:
04/11/2013
Title:
METHOD OF SCHEMATIC DRIVEN LAYOUT CREATION
29
Patent #:
8832632
Issue Dt:
09/09/2014
Application #:
13660887
Filing Dt:
10/25/2012
Title:
COMPACT ROUTING
30
Patent #:
8869084
Issue Dt:
10/21/2014
Application #:
13684496
Filing Dt:
11/24/2012
Publication #:
US20130185687
Pub Dt:
07/18/2013
Title:
PARAMETERIZED CELL LAYOUT GENERATION GUIDED BY A DESIGN RULE CHECKER
31
Patent #:
NONE
Issue Dt:
Application #:
13718979
Filing Dt:
12/18/2012
Publication #:
US20140013293
Pub Dt:
01/09/2014
Title:
HIERARCHICAL POWER MAP FOR LOW POWER DESIGN
32
Patent #:
8719762
Issue Dt:
05/06/2014
Application #:
13730543
Filing Dt:
12/28/2012
Publication #:
US20130117007
Pub Dt:
05/09/2013
Title:
METHOD AND APPARATUS FOR TURNING CUSTOM PROTOTYPE BOARDS INTO CO-SIMULATION, CO-EMULATION SYSTEMS
33
Patent #:
8875081
Issue Dt:
10/28/2014
Application #:
13778071
Filing Dt:
02/26/2013
Publication #:
US20140068542
Pub Dt:
03/06/2014
Title:
Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio
34
Patent #:
8839179
Issue Dt:
09/16/2014
Application #:
13856004
Filing Dt:
04/03/2013
Publication #:
US20130227509
Pub Dt:
08/29/2013
Title:
PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS
35
Patent #:
8832615
Issue Dt:
09/09/2014
Application #:
13891062
Filing Dt:
05/09/2013
Publication #:
US20130305207
Pub Dt:
11/14/2013
Title:
METHOD FOR DETECTING AND DEBUGGING DESIGN ERRORS IN LOW POWER IC DESIGN
36
Patent #:
8782588
Issue Dt:
07/15/2014
Application #:
14043619
Filing Dt:
10/01/2013
Publication #:
US20140033157
Pub Dt:
01/30/2014
Title:
MULTIPLE LEVEL SPINE ROUTING
37
Patent #:
9003350
Issue Dt:
04/07/2015
Application #:
14043689
Filing Dt:
10/01/2013
Publication #:
US20140033158
Pub Dt:
01/30/2014
Title:
Multiple Level Spine Routing
38
Patent #:
8990756
Issue Dt:
03/24/2015
Application #:
14086158
Filing Dt:
11/21/2013
Publication #:
US20140143747
Pub Dt:
05/22/2014
Title:
GATEWAY MODEL ROUTING WITH SLITS ON WIRES
39
Patent #:
9852251
Issue Dt:
12/26/2017
Application #:
14203300
Filing Dt:
03/10/2014
Publication #:
US20140304671
Pub Dt:
10/09/2014
Title:
MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN
40
Patent #:
9384313
Issue Dt:
07/05/2016
Application #:
14253784
Filing Dt:
04/15/2014
Publication #:
US20150294055
Pub Dt:
10/15/2015
Title:
SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS
41
Patent #:
9449138
Issue Dt:
09/20/2016
Application #:
14452368
Filing Dt:
08/05/2014
Publication #:
US20140351777
Pub Dt:
11/27/2014
Title:
PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS
42
Patent #:
10409943
Issue Dt:
09/10/2019
Application #:
14475276
Filing Dt:
09/02/2014
Publication #:
US20150067632
Pub Dt:
03/05/2015
Title:
EFFICIENT ANALOG LAYOUT PROTOTYPING BY LAYOUT REUSE WITH ROUTING PRESERVATION
43
Patent #:
9256706
Issue Dt:
02/09/2016
Application #:
14476320
Filing Dt:
09/03/2014
Publication #:
US20150067626
Pub Dt:
03/05/2015
Title:
KNOWLEDGE-BASED ANALOG LAYOUT GENERATOR
44
Patent #:
9665679
Issue Dt:
05/30/2017
Application #:
14486723
Filing Dt:
09/15/2014
Publication #:
US20150007123
Pub Dt:
01/01/2015
Title:
SYSTEMS AND METHODS FOR DESIGNING INTEGRATED CIRCUITS WITH CONSIDERATION OF HORIZONTAL AND VERTICAL WIRING DEMAND RATIOS
45
Patent #:
10192019
Issue Dt:
01/29/2019
Application #:
14496420
Filing Dt:
09/25/2014
Publication #:
US20150089465
Pub Dt:
03/26/2015
Title:
SEPARATION AND MINIMUM WIRE LENGTH CONSTRAINED MAZE ROUTING METHOD AND SYSTEM
46
Patent #:
9747406
Issue Dt:
08/29/2017
Application #:
14508205
Filing Dt:
10/07/2014
Publication #:
US20150100938
Pub Dt:
04/09/2015
Title:
SPINE ROUTING WITH MULTIPLE MAIN SPINES
47
Patent #:
9311441
Issue Dt:
04/12/2016
Application #:
14541359
Filing Dt:
11/14/2014
Publication #:
US20150143322
Pub Dt:
05/21/2015
Title:
SWITCH CELL
48
Patent #:
9305127
Issue Dt:
04/05/2016
Application #:
14541555
Filing Dt:
11/14/2014
Publication #:
US20150143310
Pub Dt:
05/21/2015
Title:
P-CELL CACHING
49
Patent #:
9881118
Issue Dt:
01/30/2018
Application #:
14576108
Filing Dt:
12/18/2014
Publication #:
US20150278421
Pub Dt:
10/01/2015
Title:
IR-AWARE SNEAK ROUTING
50
Patent #:
9721056
Issue Dt:
08/01/2017
Application #:
14576117
Filing Dt:
12/18/2014
Publication #:
US20150178441
Pub Dt:
06/25/2015
Title:
METHOD FOR WIRE WIDENING IN CIRCUIT ROUTING SYSTEM
51
Patent #:
10068040
Issue Dt:
09/04/2018
Application #:
14791216
Filing Dt:
07/02/2015
Publication #:
US20160110484
Pub Dt:
04/21/2016
Title:
METHOD AND APPARATUS FOR TRANSACTION RECORDING AND VISUALIZATION
52
Patent #:
11010528
Issue Dt:
05/18/2021
Application #:
14994048
Filing Dt:
01/12/2016
Publication #:
US20170124245
Pub Dt:
05/04/2017
Title:
KNOWLEDGE-BASED ANALOG LAYOUT GENERATOR
Assignor
1
SYNOPSYS TAIWAN CO., LTD.
Exec Dt:
03/24/2016
Assignee
1
SYNOPSYS, INC.
690 E. MIDDLEFIELD ROAD
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
ALSTON & BIRD LLP
BANK OF AMERICA PLAZA
101 SOUTH TRYON STREET, SUITE 4000
CHARLOTTE, NC 28280-4000

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