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Patent #:
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10/21/2003
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Application #:
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10044220
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Filing Dt:
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11/20/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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DENSE TRENCH MOSFET WITH DECREASED ETCH SENSITIVITY TO DEPOSITION AND ETCH PROCESSING
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11/04/2003
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10044664
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10/23/2001
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Pub Dt:
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04/24/2003
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Title:
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METHOD AND APPARATUS FOR FIELD-EFFECT TRANSISTOR CURRENT SENSING USING THE VOLTAGE DROP ACROSS DRAIN TO SOURCE RESISTANCE THAT ELIMINATES DEPENDENCIES ON TEMPERATURE OF THE FIELD-EFFECT TRANSISTOR AND/OR STATISTICAL DISTRIBUTION OF THE INITIAL VALUE OF DRAIN TO SOU
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05/20/2003
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10050428
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Filing Dt:
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01/15/2002
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Title:
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SEMICONDUCTOR DIE PACKAGE WITH IMPROVED THERMAL AND ELECTRICAL PERFORMANCE
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08/17/2004
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10050976
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01/18/2002
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07/24/2003
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Title:
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THICK BUFFER REGION DESIGN TO IMPROVE IGBT SELF-CLAMPED INDUCTIVE SWITCHING (SCIS) ENERGY DENSITY AND DEVICE MANUFACTURABILITY
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NONE
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10051740
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01/16/2002
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09/19/2002
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Title:
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Spread spectrum modulation technique for frequency synthesizers
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07/18/2006
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10052234
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01/16/2002
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07/17/2003
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Title:
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SELF-ALIGNED TRENCH MOSFETS AND METHODS FOR MAKING THE SAME
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01/06/2004
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10052945
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11/02/2001
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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SEMICONDUCTOR PACKAGES FOR SEMICONDUCTOR DEVICES
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10/28/2003
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10053891
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01/11/2002
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07/04/2002
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Title:
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METAL GATE DOUBLE DIFFUSION MOSFET WITH IMPROVED SWITCHING SPEED AND REDUCED GATE TUNNEL LEAKAGE
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09/28/2004
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10055211
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01/23/2002
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07/24/2003
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Title:
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IGBT WITH CHANNEL RESISTORS
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06/10/2003
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10071792
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02/06/2002
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08/01/2002
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Title:
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TRENCH MOSFET FORMED USING SELECTIVE EPITAXIAL GROWTH
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08/09/2005
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10077258
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02/14/2002
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08/01/2002
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Title:
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METHOD OF FORMING A TRENCH TRANSISTOR HAVING A SUPERIOR GATE DIELECTRIC
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10/15/2002
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10082944
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02/26/2002
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Pub Dt:
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08/29/2002
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Title:
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PROCESS FOR DEPOSITING AND PLANARIZING BPSG FOR DENSE TRENCH MOSFET APPLICATION
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01/27/2004
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10092692
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03/07/2002
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Pub Dt:
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09/12/2002
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Title:
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ULTRA DENSE TRENCH-GATED POWER DEVICE WITH THE REDUCED DRAIN-SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE
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09/09/2003
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10098769
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03/14/2002
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Pub Dt:
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09/18/2003
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Title:
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SUPPORTING CONTROL GATE CONNECTION ON A PACKAGE USING ADDITIONAL BUMPS
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Patent #:
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01/06/2004
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10105721
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03/25/2002
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Pub Dt:
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08/01/2002
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Title:
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FIELD COUPLED POWER MOSFET BUS ARCHITECTURE USING TRENCH TECHNOLOGY
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01/21/2003
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10108152
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03/27/2002
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Title:
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SEMICONDUCTOR PAD CONSTRUCTION ENABLING PRE-BUMP PROBING BY PLANARIZING THE POST-SORT PAD SURFACE
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11/18/2003
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10117890
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04/08/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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SUPPORTING GATE CONTACTS OVER SOURCE REGION ON MOSFET DEVICES
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10117940
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Filing Dt:
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04/05/2002
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Title:
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MOSFET DEVICE WITH MULTIPLE GATE CONTACTS OFFSET FROM GATE CONTACT AREA AND OVER SOURCE AREA
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Patent #:
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08/31/2004
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Application #:
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10138913
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Filing Dt:
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05/03/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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LOW VOLTAGE HIGH DENSITY TRENCH-GATED POWER DEVICE WITH UNIFORMLY DOPED CHANNEL AND ITS EDGE TERMINATION TECHNIQUE
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Patent #:
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02/08/2005
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10143065
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Filing Dt:
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05/09/2002
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Title:
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BANDGAP REFERENCE CIRCUIT
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Patent #:
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NONE
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Application #:
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10146863
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Filing Dt:
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05/15/2002
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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Current mirroring
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10153449
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Filing Dt:
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05/22/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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Selectable output edge rate control
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10155520
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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Differential current mode gain stage and methods of using the same
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10155554
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF ITS MANUFACTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10165747
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Filing Dt:
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06/07/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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Mid-connect architecture with point-to-point connections for high speed data transfer
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01/06/2004
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10174641
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Filing Dt:
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06/19/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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PROCESS FOR FORMING MOS-GATED POWER DEVICE HAVING SEGMENTED TRENCH AND EXTENDED DOPING ZONE
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Patent #:
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03/01/2005
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10177783
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Filing Dt:
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06/19/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR CREATING THICK OXIDE ON THE BOTTOM SURFACE OF A TRENCH STRUCTURE IN SILICON
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10196790
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07/16/2002
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Title:
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HIGHLY EFFICIENT STEP-DOWN/STEP-UP AND STEP-UP/STEP-DOWN CHARGE PUMP
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Patent #:
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Issue Dt:
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10/12/2004
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10200056
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07/18/2002
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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VERTICAL CHARGE CONTROL SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10207625
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07/29/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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ACTIVE POWER/GROUND ESD TRIGGER
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10208951
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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CAPACITIVELY COUPLED CURRENT BOOST CIRCUITRY FOR INTEGRATED VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10209110
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Filing Dt:
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07/30/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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DUAL TRENCH POWER MOSFET
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10210515
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE USING SHAPED DIE
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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10219603
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Filing Dt:
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08/14/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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POWER MOS DEVICE WITH IMPROVED GATE CHARGE PERFORMANCE
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10222481
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Filing Dt:
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08/16/2002
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Publication #:
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Pub Dt:
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02/27/2003
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Title:
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METHOD AND CIRCUIT FOR REDUCING LOSSES IN DC-DC CONVERTERS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10225636
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Filing Dt:
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08/22/2002
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Title:
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HIGH VALUE POLYSILICON RESISTOR
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10228420
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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LATERAL DEVICE WITH IMPROVED CONDUCTIVITY AND BLOCKING CONTROL
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10229602
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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12/25/2003
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Title:
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HIGH EFFICIENCY LED DRIVER
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10233248
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Filing Dt:
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08/30/2002
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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SUBSTRATE BASED UNMOLDED PACKAGE INCLUDING LEAD FRAME STRUCTURE AND SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10235249
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09/04/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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UNMOLDED PACKAGE FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10241090
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Filing Dt:
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09/10/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD AND CIRCUIT FOR PERFORMING AUTOMATIC POWER ON RESET OF AN INTEGRATED CIRCUIT
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Patent #:
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NONE
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Application #:
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10245529
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Filing Dt:
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09/17/2002
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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High performance multi-chip flip chip package
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10247461
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Filing Dt:
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09/19/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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TERMINATION STRUCTURE INCORPORATING INSULATOR IN A TRENCH
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10247464
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Filing Dt:
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09/19/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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BURIED GATE-FIELD TERMINATION STRUCTURE
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10262170
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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SEMICONDUCTOR DIE PACKAGE INCLUDING DRAIN CLIP
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10269126
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Filing Dt:
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10/03/2002
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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TRENCH GATE LATERALLY DIFFUSED MOSFET DEVICES AND METHODS FOR MAKING SUCH DEVICES
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10269244
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Filing Dt:
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10/11/2002
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Title:
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SCHOTTKY RECTIFIER WITH INSULATION-FILLED TRENCHES AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10271654
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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THIN, THERMALLY ENHANCED FLIP CHIP IN A LEADED MOLDED PACKAGE
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Patent #:
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12/14/2004
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Application #:
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10278224
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10/22/2002
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Pub Dt:
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05/01/2003
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Title:
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QUICK PUNCH THROUGH IGBT HAVING GATE-CONTROLLABLE DI/DT AND REDUCED EMI DURING INDUCTIVE TURN OFF
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02/15/2005
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Application #:
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10280313
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10/25/2002
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Pub Dt:
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05/08/2003
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Title:
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TRIGGERING OF AN ESD NMOS THROUGH THE USE OF AN N-TYPE BURIED LAYER
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Issue Dt:
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08/24/2004
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Application #:
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10282569
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Filing Dt:
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10/29/2002
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Publication #:
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Pub Dt:
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04/29/2004
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Title:
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LOW POWER LOW VOLTAGE DIFFERENTIAL SIGNAL RECEIVER WITH IMPROVED SKEW AND JITTER PERFORMANCE
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Patent #:
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11/07/2006
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10288982
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11/05/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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TRENCH STRUCTURE HAVING ONE OR MORE DIODES EMBEDDED THEREIN ADJACENT A PN JUNCTION
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Patent #:
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08/24/2004
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10292119
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11/12/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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FAILSAFE DIFFERENTIAL AMPLIFIER CIRCUIT
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Issue Dt:
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08/31/2004
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10301375
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11/20/2002
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DYNAMICALLY CONTROLLED AMPLIFIER
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08/24/2004
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Application #:
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10301465
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Filing Dt:
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11/21/2002
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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ACTIVE VOLTAGE LEVEL BUS SWITCH (OR PASS GATE) TRANSLATOR
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10309661
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Filing Dt:
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12/03/2002
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Publication #:
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Pub Dt:
|
07/03/2003
| | | | |
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Title:
|
HIGH PERFORMANCE MULTI-CHIP FLIP CHIP PACKAGE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10310374
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Filing Dt:
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12/04/2002
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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Device authentication system and method
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Patent #:
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Issue Dt:
|
03/22/2005
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Application #:
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10315517
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Filing Dt:
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12/10/2002
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Publication #:
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Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE WITH IMPROVED LDMOS DESIGN
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Patent #:
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Issue Dt:
|
06/14/2005
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Application #:
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10315719
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Filing Dt:
|
12/10/2002
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Publication #:
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Pub Dt:
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07/31/2003
| | | | |
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Title:
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METHOD OF ISOLATING THE CURRENT SENSE ON POWER DEVICES WHILE MAINTAINING A CONTINUOUS STRIPE CELL
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Patent #:
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Issue Dt:
|
10/19/2004
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Application #:
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10330741
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Filing Dt:
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12/26/2002
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Publication #:
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Pub Dt:
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07/01/2004
| | | | |
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Title:
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MULTICHIP MODULE INCLUDING SUBSTRATE WITH AN ARRAY OF INTERCONNECT STRUCTURES
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Patent #:
|
|
Issue Dt:
|
08/03/2004
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Application #:
|
10342634
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Filing Dt:
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01/15/2003
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|
Title:
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A PROCESS OF COMPENSATING FOR LAYER THICKNESS BY DETERMINING PARAMETERS ON DIFFERENT SURFACE AREAS OF A SUBSTRATE
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Patent #:
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|
Issue Dt:
|
12/14/2004
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Application #:
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10346682
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Filing Dt:
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01/17/2003
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Publication #:
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Pub Dt:
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07/24/2003
| | | | |
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Title:
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SEMICONDUCTOR DIE PACKAGE WITH SEMICONDUCTOR DIE HAVING SIDE ELECTRICAL CONNECTION
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|
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Patent #:
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|
Issue Dt:
|
01/18/2005
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Application #:
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10346807
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Filing Dt:
|
01/17/2003
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Publication #:
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Pub Dt:
|
02/19/2004
| | | | |
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Title:
|
FLYBACK CONVERTER
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|
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Patent #:
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|
Issue Dt:
|
12/07/2004
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Application #:
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10347254
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Filing Dt:
|
01/17/2003
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|
Publication #:
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Pub Dt:
|
07/10/2003
| | | | |
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF ITS MANUFACTURE
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Patent #:
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|
Issue Dt:
|
03/15/2005
|
Application #:
|
10349131
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Filing Dt:
|
01/21/2003
|
|
Title:
|
SEMICONDUCTOR DIE PACKAGE PROCESSABLE AT THE WAFER LEVEL
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|
|
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|
Patent #:
|
|
Issue Dt:
|
04/26/2005
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Application #:
|
10355317
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Filing Dt:
|
01/31/2003
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|
Publication #:
|
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Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
HIGH VALUE SPLIT POLY P-RESISTOR WITH LOW STANDARD DEVIATION
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Patent #:
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|
Issue Dt:
|
08/09/2005
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Application #:
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10368253
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Filing Dt:
|
02/18/2003
|
|
Title:
|
METHOD AND STRUCTURE FOR BICMOS ISOLATED NMOS TRANSISTOR
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Patent #:
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Issue Dt:
|
08/23/2005
|
Application #:
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10370047
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Filing Dt:
|
02/18/2003
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|
Publication #:
|
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Pub Dt:
|
02/05/2004
| | | | |
|
Title:
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SOFT START TECHNIQUES FOR CONTROL LOOPS THAT REGULATE DC/DC CONVERTERS
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Patent #:
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|
Issue Dt:
|
01/04/2005
|
Application #:
|
10383389
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Filing Dt:
|
03/07/2003
|
|
Title:
|
ENVELOPING CURVES GENERATOR CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
03/02/2004
|
Application #:
|
10385765
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Filing Dt:
|
03/11/2003
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|
Publication #:
|
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Pub Dt:
|
09/11/2003
| | | | |
|
Title:
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DRAIN ACTIVATED/DEACTIVATED AC COUPLED BANDPASS RF SWITCH
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Patent #:
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Issue Dt:
|
09/18/2007
|
Application #:
|
10386211
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Filing Dt:
|
03/10/2003
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|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
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DUAL METAL STUD BUMPING FOR FLIP CHIP APPLICATIONS
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|
Patent #:
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|
Issue Dt:
|
05/04/2004
|
Application #:
|
10386621
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Filing Dt:
|
03/11/2003
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|
Publication #:
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Pub Dt:
|
09/18/2003
| | | | |
|
Title:
|
WAFER-LEVEL COATED COPPER STUD BUMPS
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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10391126
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Filing Dt:
|
03/17/2003
|
|
Publication #:
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Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
Power MOS device with improved gate charge performance
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Patent #:
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|
Issue Dt:
|
12/06/2005
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Application #:
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10395460
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Filing Dt:
|
03/24/2003
|
|
Title:
|
QUASI SELF-ALIGNED SINGLE POLYSILICON BIPOLAR ACTIVE DEVICE WITH INTENTIONAL EMITTER WINDOW UNDERCUT
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/28/2006
|
Application #:
|
10395499
|
Filing Dt:
|
03/24/2003
|
|
Title:
|
SINGLE POLISILICON EMITTER BIPOLAR JUNCTION TRANSISTOR PROCESSING TECHNIQUE USING CUMULATIVE PHOTO RESIST APPLICATION AND PATTERNING
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Patent #:
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|
Issue Dt:
|
01/29/2008
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Application #:
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10397436
|
Filing Dt:
|
03/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
|
Title:
|
PACKAGING SYSTEM FOR SEMICONDUCTOR DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10406334
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Filing Dt:
|
04/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
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SWITCHABLE AMPLIFIER CIRCUIT HAVING REDUCED SHUTDOWN CURRENT
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Patent #:
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|
Issue Dt:
|
10/26/2004
|
Application #:
|
10408471
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Filing Dt:
|
04/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
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POWER CIRCUITRY WITH A THERMIONIC COOLING SYSTEM
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/15/2005
|
Application #:
|
10411688
|
Filing Dt:
|
04/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
|
Title:
|
LEAD FRAME STRUCTURE WITH APERTURE OR GROOVE FOR FLIP CHIP IN A LEADED MOLDED PACKAGE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/21/2004
|
Application #:
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10412448
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Filing Dt:
|
04/28/2020
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|
Publication #:
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|
Pub Dt:
|
10/16/2003
| | | | |
|
Title:
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PLL FOR CLOCK RECOVERY WITH INITIALIZATION SEQUENCE
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Patent #:
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Issue Dt:
|
10/17/2006
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Application #:
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10413668
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Filing Dt:
|
04/14/2003
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|
Publication #:
|
|
Pub Dt:
|
10/16/2003
| | | | |
|
Title:
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ROBUST LEADED MOLDED PACKAGES AND METHODS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
|
12/28/2004
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Application #:
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10413796
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Filing Dt:
|
04/14/2003
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|
Publication #:
|
|
Pub Dt:
|
10/23/2003
| | | | |
|
Title:
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STRUCTURE OF INTEGRATED TRACE OF CHIP PACKAGE
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|
|
|
Patent #:
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|
Issue Dt:
|
05/10/2005
|
Application #:
|
10419281
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Filing Dt:
|
04/17/2003
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|
Publication #:
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|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
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Method For Producing A Semiconductor Die Package Using Leadframe With Locating Holes
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Patent #:
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|
Issue Dt:
|
06/08/2004
|
Application #:
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10431746
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Filing Dt:
|
05/08/2003
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|
Publication #:
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|
Pub Dt:
|
09/18/2003
| | | | |
|
Title:
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SUPPORTING CONTROL GATE CONNECTION ON A PACKAGE USING ADDITIONAL BUMPS
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Patent #:
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|
Issue Dt:
|
03/08/2005
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Application #:
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10435831
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Filing Dt:
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05/12/2003
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Publication #:
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Pub Dt:
|
11/13/2003
| | | | |
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Title:
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CROSS POINT SWITCH WITH SERIALIZER AND DESERIALIZER FUNCTIONS
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Patent #:
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Issue Dt:
|
03/29/2005
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Application #:
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10438349
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Filing Dt:
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05/14/2003
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|
Publication #:
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|
Pub Dt:
|
11/18/2004
| | | | |
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Title:
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ESD PROTECTION FOR SEMICONDUCTOR PRODUCTS
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Patent #:
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Issue Dt:
|
07/12/2005
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Application #:
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10442670
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
|
11/25/2004
| | | | |
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Title:
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STRUCTURE AND METHOD FOR FORMING A TRENCH MOSFET HAVING SELF-ALIGNED FEATURES
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Patent #:
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Issue Dt:
|
08/23/2005
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Application #:
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10447629
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Filing Dt:
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05/28/2003
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
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Title:
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COMMON MODE BIAS CONTROL LOOP FOR OUTPUT STAGES
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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10459916
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Filing Dt:
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06/11/2003
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Publication #:
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Pub Dt:
|
02/05/2004
| | | | |
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Title:
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Mid-connect architecture with point-to-point connections for high speed data transfer
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Patent #:
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Issue Dt:
|
06/29/2004
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Application #:
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10460075
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Filing Dt:
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06/12/2003
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Title:
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METHOD OF REDUCING THE PROPAGATION DELAY AND PROCESS AND TEMPERATURE EFFECTS ON A BUFFER
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Patent #:
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Issue Dt:
|
03/01/2005
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Application #:
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10602336
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Filing Dt:
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06/23/2003
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Publication #:
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Pub Dt:
|
07/08/2004
| | | | |
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Title:
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METHOD FOR MAKING POWER CHIP SCALE PACKAGE
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Patent #:
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|
Issue Dt:
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08/10/2004
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Application #:
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10602798
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Filing Dt:
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06/24/2003
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Title:
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BUS HOLD CIRCUIT WITH POWER-DOWN AND OVER-VOLTAGE TOLERANCE
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10607633
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Filing Dt:
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06/27/2003
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Publication #:
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Pub Dt:
|
03/25/2004
| | | | |
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Title:
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FLIP CHIP IN LEADED MOLDED PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10618067
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Filing Dt:
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07/11/2003
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Publication #:
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Pub Dt:
|
06/03/2004
| | | | |
|
Title:
|
DENSE TRENCH MOSFET WITH DECREASED ETCH SENSITIVITY TO DEPOSITION AND ETCH PROCESSING
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|
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
10618113
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Filing Dt:
|
07/11/2003
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|
Publication #:
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Pub Dt:
|
08/11/2005
| | | | |
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Title:
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Wafer-level chip scale package and method for fabricating and using the same
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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10630249
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Filing Dt:
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07/30/2003
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Publication #:
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Pub Dt:
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07/29/2004
| | | | |
|
Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF ITS MANUFACTURE
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Patent #:
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|
Issue Dt:
|
03/22/2005
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Application #:
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10640742
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Filing Dt:
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08/14/2003
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Publication #:
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Pub Dt:
|
06/17/2004
| | | | |
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Title:
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METHOD AND APPARATUS FOR IMPROVED MOS GATING TO REDUCE MILLER CAPACITANCE AND SWITCHING LOSSES
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10645033
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Filing Dt:
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08/21/2003
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|
Publication #:
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Pub Dt:
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04/29/2004
| | | | |
|
Title:
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LOW VOLTAGE, LOW POWER DIFFERENTIAL RECEIVER
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10645408
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Filing Dt:
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08/21/2003
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Publication #:
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Pub Dt:
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04/29/2004
| | | | |
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Title:
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LOW VOLTAGE DIFFERENTIAL IN DIFFERENTIAL OUT RECEIVER
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10660866
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Filing Dt:
|
09/11/2003
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|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
|
Title:
|
FLIP CHIP SUBSTRATE DESIGN
|
|
