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Total properties:
17
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10871311
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Filing Dt:
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06/18/2004
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
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DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS
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Patent #:
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Issue Dt:
|
01/04/2011
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Application #:
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10871329
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Filing Dt:
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06/18/2004
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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SYSTEM OF HARDWARE OBJECTS
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10871347
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Filing Dt:
|
06/18/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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DATA INTERFACE REGISTER STRUCTURE WITH REGISTERS FOR DATA, VALIDITY, GROUP MEMBERSHIP INDICATOR, AND READY TO ACCEPT NEXT MEMBER SIGNAL
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Patent #:
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Issue Dt:
|
08/05/2008
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Application #:
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11326701
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Filing Dt:
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01/06/2006
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Publication #:
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Pub Dt:
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06/01/2006
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Title:
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ASYNCHRONOUS COMMUNICATION AMONG HARDWARE OBJECT NODES IN IC WITH RECEIVE AND SEND PORTS PROTOCOL REGISTERS USING TEMPORARY REGISTER BYPASS SELECT FOR VALIDITY INFORMATION
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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11340957
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Filing Dt:
|
01/27/2006
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Publication #:
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Pub Dt:
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02/01/2007
| | | | |
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Title:
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SYSTEM OF VIRTUAL DATA CHANNELS IN AN INTEGRATED CIRCUIT
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|
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Patent #:
|
NONE
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Issue Dt:
|
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Application #:
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11458061
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Filing Dt:
|
07/17/2006
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Publication #:
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Pub Dt:
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02/15/2007
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Title:
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SYSTEM OF VIRTUAL DATA CHANNELS ACROSS CLOCK BOUNDARIES IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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11460231
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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03/22/2007
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Title:
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CLOCK GENERATION FOR MULTIPLE CLOCK DOMAINS
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|
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Patent #:
|
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Issue Dt:
|
07/29/2008
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Application #:
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11466083
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Filing Dt:
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08/21/2006
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Publication #:
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Pub Dt:
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12/14/2006
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Title:
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IC COMPRISING NETWORK OF MICROPROCESSORS COMMUNICATING DATA MESSAGES ALONG ASYNCHRONOUS CHANNEL SEGMENTS USING PORTS INCLUDING VALIDITY AND ACCEPT SIGNAL REGISTERS AND WITH SPLIT/JOIN CAPABILITY
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Patent #:
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|
Issue Dt:
|
03/02/2010
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Application #:
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11466337
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Filing Dt:
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08/22/2006
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Publication #:
|
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Pub Dt:
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12/14/2006
| | | | |
|
Title:
|
DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS
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|
|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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11557478
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Filing Dt:
|
11/07/2006
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|
Publication #:
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Pub Dt:
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05/31/2007
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Title:
|
RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION NETWORK
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|
|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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11672450
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Filing Dt:
|
02/07/2007
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|
Publication #:
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Pub Dt:
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07/19/2007
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Title:
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PROCESSOR HAVING MULTIPLE INSTRUCTION SOURCES AND EXECUTION MODES
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Patent #:
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Issue Dt:
|
08/18/2009
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Application #:
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11673986
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Filing Dt:
|
02/12/2007
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|
Publication #:
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|
Pub Dt:
|
08/02/2007
| | | | |
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Title:
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INTERACTIVE DEBUG SYSTEM FOR MULTIPROCESSOR ARRAY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/28/2010
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Application #:
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11676206
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Filing Dt:
|
02/16/2007
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Publication #:
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Pub Dt:
|
08/02/2007
| | | | |
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Title:
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MULTI-FREQUENCY DEBUG NETWORK FOR A MULTIPROCESSOR ARRAY
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|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
11733135
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Filing Dt:
|
04/09/2007
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|
Publication #:
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|
Pub Dt:
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10/11/2007
| | | | |
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Title:
|
MOTION COMPENSATION IN DIGITAL VIDEO
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11735390
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Filing Dt:
|
04/13/2007
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|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
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Title:
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DATA PIPELINE TRANSPORT SYSTEM
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12018045
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Filing Dt:
|
01/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2008
| | | | |
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Title:
|
SYSTEM FOR CONFIGURING A PROCESSOR ARRAY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
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Application #:
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12018062
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Filing Dt:
|
01/22/2008
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|
Publication #:
|
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Pub Dt:
|
09/18/2008
| | | | |
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Title:
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SYSTEM FOR RECONFIGURING A PROCESSOR ARRAY
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|
