Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 051301/0387 | |
| Pages: | 8 |
| | Recorded: | 12/16/2019 | | |
Attorney Dkt #: | 5059-500027 |
Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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04/21/2020
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Application #:
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15874727
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Filing Dt:
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01/18/2018
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Title:
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METHODS AND SYSTEMS FOR GENERATING INTERRUPTS BY A RESPONSE DIRECT MEMORY ACCESS MODULE
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Patent #:
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Issue Dt:
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03/17/2020
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Application #:
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15912336
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Filing Dt:
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03/05/2018
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Title:
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METHODS AND SYSTEMS FOR TRACKING A VIRTUAL MEMORY OF A VIRTUAL MACHINE
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Patent #:
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Issue Dt:
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11/23/2021
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Application #:
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16054797
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Filing Dt:
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08/03/2018
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Publication #:
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Pub Dt:
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02/06/2020
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Title:
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CHAINED LOOKUPS AND COUNTING IN A NETWORK SWITCH
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Patent #:
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Issue Dt:
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09/07/2021
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Application #:
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16110957
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Filing Dt:
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08/23/2018
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Publication #:
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Pub Dt:
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05/09/2019
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Title:
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Methods And Apparatus For Simultaneous Multiprotocol Processing of Different Radio Standards Using A Common Pipeline
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Patent #:
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Issue Dt:
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08/11/2020
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Application #:
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16146539
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Filing Dt:
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09/28/2018
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Title:
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METHODS AND SYSTEMS FOR LOAD BALANCING IN NETWORK DEVICES
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Patent #:
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Issue Dt:
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09/14/2021
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Application #:
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16264386
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Filing Dt:
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01/31/2019
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Publication #:
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Pub Dt:
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08/06/2020
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Title:
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LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN MULTI-CHIP PROCESSING SYSTEM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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16568698
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Filing Dt:
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09/12/2019
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Publication #:
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Pub Dt:
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03/18/2021
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Title:
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METHOD OF IMPROVING L1 ICACHE PERFORMANCE WITH LARGE PROGRAMS
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Patent #:
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Issue Dt:
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07/12/2022
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Application #:
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16589527
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Filing Dt:
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10/01/2019
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Publication #:
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Pub Dt:
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04/01/2021
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Title:
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MERGE EXECUTION UNIT FOR MICROINSTRUCTIONS
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Assignee
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5488 MARVELL LN |
SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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HARNESS, DICKEY & PIERCE, P.L.C.
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P.O. BOX 828
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BLOOMFIELD HILLS, MI 48303
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