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Reel/Frame:059094/0393   Pages: 4
Recorded: 02/24/2022
Attorney Dkt #:TSMP20210350US01
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
04/23/2024
Application #:
17532204
Filing Dt:
11/22/2021
Publication #:
Pub Dt:
12/22/2022
Title:
GATE STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING SAME
Assignors
1
Exec Dt:
07/28/2021
2
Exec Dt:
11/30/2021
3
Exec Dt:
07/29/2021
4
Exec Dt:
07/28/2021
Assignee
1
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
SLATER MATSIL, LLP/TSMC
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252

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