Total properties:
129
Page
2
of
2
Pages:
1 2
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09268605
|
Filing Dt:
|
03/15/1999
|
Title:
|
METHOD FOR FABRICATING ELECTROSTATIC DISCHARGE PROTECTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09283530
|
Filing Dt:
|
04/01/1999
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
Title:
|
WAFER TRENCH ARTICLE AND PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09283531
|
Filing Dt:
|
04/01/1999
|
Title:
|
HIGH DENSITY MOS-GATED POWER DEVICE AND PROCESS FOR FORMING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09283536
|
Filing Dt:
|
04/01/1999
|
Publication #:
|
|
Pub Dt:
|
05/24/2001
| | | | |
Title:
|
POWER TRENCH MOS-GATED DEVICE AND PROCESS FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09303270
|
Filing Dt:
|
04/30/1999
|
Title:
|
POWER MOS DEVICE WITH INCREASED CHANNEL WIDTH AND PROCESS FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09307879
|
Filing Dt:
|
05/10/1999
|
Title:
|
PROCESS FOR FORMING MOS-GATED DEVICES HAVING SELF-ALIGNED TRENCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
09307896
|
Filing Dt:
|
05/10/1999
|
Title:
|
LASER DECAPSULATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09314323
|
Filing Dt:
|
05/19/1999
|
Title:
|
MOS-GATED POWER DEVICE HAVING EXTENDED TRENCH AND DOPING ZONE AND PROCESS FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
09316580
|
Filing Dt:
|
05/21/1999
|
Title:
|
BONDED WAFER WITH METAL SILICIDATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09318334
|
Filing Dt:
|
05/25/1999
|
Title:
|
TRENCH-GATED DEVICE HAVING TRENCH WALLS FORMED BY SELECTIVE EPITAXIAL GROWTH AND PROCESS FOR FORMING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09324553
|
Filing Dt:
|
06/03/1999
|
Title:
|
LOW VOLTAGE DUAL-WELL MOS DEVICE HAVING HIGH RUGGEDNESS, LOW ON-RESISTANCE, AND IMPROVED BODY DIODE REVERSE RECOVERY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09330437
|
Filing Dt:
|
06/11/1999
|
Title:
|
POWER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09334098
|
Filing Dt:
|
06/16/1999
|
Title:
|
POWER MODULE WITH LOWERED INDUCTANCE AND REDUCED VOLTAGE OVERSHOOTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09334835
|
Filing Dt:
|
06/17/1999
|
Title:
|
SELF-SUPPORTED ULTRATHIN SILICON WAFER PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09334987
|
Filing Dt:
|
06/17/1999
|
Title:
|
DEFECT GETTERING BY INDUCED STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09334998
|
Filing Dt:
|
06/17/1999
|
Title:
|
CURRENT-CONTROLLED CARRIER TRACKING FILTER FOR IMPROVED SPURIOU SIGNAL SUPPRESSION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09335113
|
Filing Dt:
|
06/17/1999
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
SC-2 BASED PRE-THERMAL TREATMENT WAFER CLEANING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09338891
|
Filing Dt:
|
06/23/1999
|
Title:
|
SEMICONDUCTOR DEVICE GATE STRUCTURE FOR THERMAL OVERLOAD PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09339274
|
Filing Dt:
|
06/23/1999
|
Title:
|
METHOD OF FORMING AN INTEGRATED RESISTIVE CONTACTS WITH MOBILITY SPOILING IONS INCLUDING HIGH RESISTIVITY CONTACTS AND LOW RESISTIVITY SILICIDE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09339356
|
Filing Dt:
|
06/24/1999
|
Title:
|
BACKMETAL DRAIN TERMINAL WITH LOW STRESS AND THERMAL RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09342376
|
Filing Dt:
|
06/29/1999
|
Title:
|
DUAL MODE CLASS D AMPLIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09342583
|
Filing Dt:
|
06/29/1999
|
Title:
|
RAKE RECEIVER WITH EMBEDDED DECISION FEEDBACK EQUALIZER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09342948
|
Filing Dt:
|
06/29/1999
|
Title:
|
BRUSHLESS MULTIPASS SILICON WAFER CLEANING PROCESS FOR POST CHEMICAL MECHANICAL POLISHING USING IMMERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
09343845
|
Filing Dt:
|
06/30/1999
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
METHOD OF MANUFACTURING A PLATED ELECTRONIC TERMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09344867
|
Filing Dt:
|
06/28/1999
|
Title:
|
POTTED TRANSDUCER ARRAY WITH MATCHING NETWORK IN A MULTIPLE PASS CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09345261
|
Filing Dt:
|
06/30/1999
|
Title:
|
METHOD FOR MAKING A DIFFUSED BACK-SIDE LAYER ON A BONDED-WAFER WITH A THICK BOND OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09345929
|
Filing Dt:
|
07/01/1999
|
Title:
|
LOW TEMPERATURE COEFFICIENT RESISTOR (TCRL)
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09345930
|
Filing Dt:
|
07/01/1999
|
Title:
|
POWER SEMICONDUCTOR MOUNTING PACKAGE CONTAINING BALL GRID ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09350575
|
Filing Dt:
|
07/09/1999
|
Title:
|
PROCESS FOR FORMING VERTICAL SEMICONDUCTOR DEVICE HAVING INCREASED SOURCE CONTACT AREA
|
|