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Patent Assignment Details
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Reel/Frame:012653/0397   Pages: 7
Recorded: 03/08/2002
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 16
1
Patent #:
Issue Dt:
07/12/1994
Application #:
07910029
Filing Dt:
07/23/1992
Title:
TEST CHIP FOR SEMICONDUCTOR FAULT ANALYSIS
2
Patent #:
Issue Dt:
06/14/1994
Application #:
07930615
Filing Dt:
09/30/1992
Title:
SPIN-ON GLASS PROCESSING TECHNIQUE FOR THE FABRICATION OF SEMICONDUCTOR DEVICES
3
Patent #:
Issue Dt:
11/15/1994
Application #:
07962214
Filing Dt:
01/26/1993
Title:
SOG WITH MOISTURE RESISTANT PROTECTIVE CAPPING LAYER
4
Patent #:
Issue Dt:
11/28/1995
Application #:
07965264
Filing Dt:
01/26/1993
Title:
MOISTURE-FREE SOG PROCESS
5
Patent #:
Issue Dt:
10/10/1995
Application #:
08039485
Filing Dt:
04/30/1993
Title:
MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG
6
Patent #:
Issue Dt:
09/05/1995
Application #:
08078166
Filing Dt:
06/21/1993
Title:
PREVENTING OF VIA POISONING BY GLOW DISCHARGE INDUCED DESORPTION
7
Patent #:
Issue Dt:
07/30/1996
Application #:
08196078
Filing Dt:
02/25/1994
Title:
HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES
8
Patent #:
Issue Dt:
12/24/1996
Application #:
08313091
Filing Dt:
09/30/1994
Title:
METHOD OF PREPARING ANTIMONY DOPED SEMICONDUCTOR WITH INTRINSIC GETTERING
9
Patent #:
Issue Dt:
05/05/1998
Application #:
08543497
Filing Dt:
10/16/1995
Title:
STABILIZATION OF THE INTERFACE BETWEEN ALUMINUM AND TITANIUM NITRIDE
10
Patent #:
Issue Dt:
08/10/1999
Application #:
08666256
Filing Dt:
06/20/1996
Title:
SUBSTRTAE PROCESSING APPARATUS WITH NON-EVAPORABLE GETTER PUMP
11
Patent #:
Issue Dt:
07/14/1998
Application #:
08666257
Filing Dt:
06/20/1996
Title:
REACTIVE PVD WITH NEG PUMP
12
Patent #:
Issue Dt:
06/13/2000
Application #:
08794441
Filing Dt:
02/04/1997
Title:
INTEGRATED PROCESSING FOR AN ETCH MODULE USING A HARD MASK TECHNIQUE
13
Patent #:
Issue Dt:
10/03/2000
Application #:
08979956
Filing Dt:
11/26/1997
Title:
STABILIZATION OF THE INTERFACE BETWEEN TIN AND A1 ALLOYS
14
Patent #:
Issue Dt:
10/17/2000
Application #:
09010191
Filing Dt:
01/21/1998
Title:
METHOD OF PROTECTING LIGHT SENSITIVE REGIONS OF INTEGRATED CIRCUITS
15
Patent #:
Issue Dt:
07/31/2001
Application #:
09236101
Filing Dt:
01/25/1999
Title:
METHOD OF FORMING CAPACITORS ON INTEGRATED CIRCUIT
16
Patent #:
Issue Dt:
07/04/2000
Application #:
09314105
Filing Dt:
05/19/1999
Title:
METHOD OF FORMING CAPACITORS IN A SEMICONDUCTOR DEVICE
Assignor
1
Exec Dt:
07/25/2001
Assignee
1
400 MARCH ROAD
OTTAWA, ONTARIO K2K 3
Correspondence name and address
MARKS & CLERK
GEORGE M. MACGREGOR
P.O. BOX 957, STATION B
OTTAWA, ON K1P 5S7

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