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Total properties:
37
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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10309554
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Filing Dt:
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12/03/2002
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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METHOD AND SYSTEM FOR INSTRUCTION-SET ARCHITECTURE SIMULATION USING JUST IN TIME COMPILATION
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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10641457
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Filing Dt:
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08/14/2003
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Title:
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AUTOMATIC GENERATION OF STRUCTURE AND CONTROL PATH USING HARDWARE DESCRIPTION LANGUAGE
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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10700600
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Filing Dt:
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11/03/2003
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Title:
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METHOD OF PROTOCOL CONVERSION BETWEEN SYNCHRONOUS PROTOCOLS THAT ARE SUITABLE FOR SYNTHESIS
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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10700601
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Filing Dt:
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11/03/2003
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Title:
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AUTOMATIC GENERATION OF TRANSACTION LEVEL BUS SIMULATION INSTRUCTIONS FROM BUS PROTOCOL
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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10815228
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Filing Dt:
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03/30/2004
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Title:
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Generation of compiler description from architecture description
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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10816328
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Filing Dt:
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03/31/2004
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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RESOURCE MANAGEMENT IN A MULTICORE ARCHITECTURE
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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10936230
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Filing Dt:
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09/07/2004
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Title:
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Generation of instruction set from architecture description
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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10937068
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Filing Dt:
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09/08/2004
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Title:
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DETERMINING LARGE-SCALE FINITE STATE MACHINES USING CONSTRAINT RELAXATION
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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10937645
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Filing Dt:
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09/08/2004
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Title:
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LARGE SCALE FINITE STATE MACHINES
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Patent #:
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|
Issue Dt:
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05/19/2015
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Application #:
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10941457
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Filing Dt:
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09/14/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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DEBUG IN A MULTICORE ARCHITECTURE
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Patent #:
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|
Issue Dt:
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04/02/2013
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Application #:
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10976402
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Filing Dt:
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10/28/2004
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Title:
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TRANSACTION LEVEL MODEL SYNTHESIS
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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11066841
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Filing Dt:
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02/25/2005
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Publication #:
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Pub Dt:
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08/31/2006
| | | | |
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Title:
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INTERFACE CONVERTER FOR UNIFIED VIEW OF MULTIPLE COMPUTER SYSTEM SIMULATIONS
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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11066945
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Filing Dt:
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02/25/2005
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Publication #:
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|
Pub Dt:
|
08/31/2006
| | | | |
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Title:
|
METHOD AND SYSTEM FOR DYNAMICALLY ADJUSTING SPEED VERSUS ACCURACY OF COMPUTER PLATFORM SIMULATION
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|
|
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Patent #:
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|
Issue Dt:
|
08/31/2010
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Application #:
|
11069496
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Filing Dt:
|
02/28/2005
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Title:
|
PROCESSOR/MEMORY CO-EXPLORATION AT MULTIPLE ABSTRACTION LEVELS
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|
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Patent #:
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|
Issue Dt:
|
10/11/2011
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Application #:
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11069616
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Filing Dt:
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02/28/2005
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|
Publication #:
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Pub Dt:
|
08/31/2006
| | | | |
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Title:
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EFFICIENT CLOCK MODELS AND THEIR USE IN SIMULATION
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|
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Patent #:
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Issue Dt:
|
04/01/2014
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Application #:
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11096184
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Filing Dt:
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03/30/2005
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Title:
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SCHEDULING OF INSTRUCTIONS
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Patent #:
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|
Issue Dt:
|
12/25/2007
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Application #:
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11139373
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Filing Dt:
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05/26/2005
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Title:
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METHOD AND DEVICE FOR SIMULATOR GENERATION BASED ON SEMANTIC TO BEHAVIORAL TRANSLATION
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|
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Patent #:
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|
Issue Dt:
|
03/08/2016
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Application #:
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11140353
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Filing Dt:
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05/26/2005
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Title:
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COMPILER RETARGETING BASED ON INSTRUCTION SEMANTIC MODELS
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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11145240
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Filing Dt:
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06/03/2005
|
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Title:
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METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF INSTRUCTION-SET DOCUMENTATION FROM AN ABSTRACT PROCESSOR MODEL DESCRIBED USING A HIERARCHICAL ARCHITECTURAL DESCRIPTION LANGUAGE
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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11356578
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Filing Dt:
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02/17/2006
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Publication #:
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Pub Dt:
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06/28/2007
| | | | |
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Title:
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SCALABLE LANGUAGE INFRASTRUCTURE FOR ELECTRONIC SYSTEM LEVEL TOOLS
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Patent #:
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|
Issue Dt:
|
06/23/2015
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Application #:
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11388484
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Filing Dt:
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03/23/2006
|
|
Title:
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User interface for facilitation of high level generation of processor extensions
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|
Patent #:
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|
Issue Dt:
|
05/20/2014
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Application #:
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11540146
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Filing Dt:
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09/29/2006
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|
Publication #:
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Pub Dt:
|
09/20/2007
| | | | |
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Title:
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Scheduling in a multicore processor
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|
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|
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Patent #:
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|
Issue Dt:
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09/10/2013
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Application #:
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11541315
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Filing Dt:
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09/29/2006
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|
Publication #:
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Pub Dt:
|
09/20/2007
| | | | |
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Title:
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MANAGING POWER CONSUMPTION IN A MULTICORE PROCESSOR
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|
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Patent #:
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|
Issue Dt:
|
11/28/2017
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Application #:
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11584402
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Filing Dt:
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10/19/2006
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Publication #:
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Pub Dt:
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06/28/2007
| | | | |
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Title:
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Dynamic host code generation from architecture description for fast simulation
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|
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Patent #:
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|
Issue Dt:
|
07/04/2017
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Application #:
|
11607243
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Filing Dt:
|
12/01/2006
|
|
Title:
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TECHNIQUES FOR CREATING AND USING A HIERARCHICAL DATA STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
04/19/2016
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Application #:
|
11637374
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Filing Dt:
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12/11/2006
|
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Title:
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System and method for stopping integrated circuit simulation
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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11637376
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Filing Dt:
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12/11/2006
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Title:
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TECHNIQUES FOR COORDINATING AND CONTROLLING DEBUGGERS IN A SIMULATION ENVIRONMENT
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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11637418
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Filing Dt:
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12/11/2006
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Title:
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Method and system for instruction set simulation with concurrent attachment of multiple debuggers
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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11707412
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Filing Dt:
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02/16/2007
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Title:
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SIMULATION WITH DYNAMIC RUN-TIME ACCURACY ADJUSTMENT
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Patent #:
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Issue Dt:
|
03/01/2011
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Application #:
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11707413
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Filing Dt:
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02/16/2007
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Publication #:
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Pub Dt:
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08/16/2007
| | | | |
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Title:
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RUN-TIME SWITCHING FOR SIMULATION WITH DYNAMIC RUN-TIME ACCURACY ADJUSTMENT
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11824880
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Filing Dt:
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07/02/2007
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Title:
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CACHING INFORMATION TO MAP SIMULATION ADDRESSES TO HOST ADDRESSES IN COMPUTER SYSTEM SIMULATIONS
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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12001238
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Filing Dt:
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12/10/2007
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Title:
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SYSTEM AND METHOD OF DEBUGGING MULTI-THREADED PROCESSES
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Patent #:
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Issue Dt:
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03/12/2013
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Application #:
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12030192
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Filing Dt:
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02/12/2008
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Title:
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SIMULATION CONTROL TECHNIQUES
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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12777526
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Filing Dt:
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05/11/2010
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Publication #:
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Pub Dt:
|
05/19/2011
| | | | |
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Title:
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INTERFACE CONVERTER FOR UNIFIED VIEW OF MULTIPLE COMPUTER SYSTEM SIMULATIONS
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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12819981
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Filing Dt:
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06/21/2010
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Publication #:
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Pub Dt:
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02/10/2011
| | | | |
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Title:
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METHOD FOR DYNAMICALLY ADJUSTING SPEED VERSUS ACCURACY OF COMPUTER PLATFORM SIMULATION
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12840211
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Filing Dt:
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07/20/2010
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Title:
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LARGE SCALE FINITE STATE MACHINES
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12871884
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Filing Dt:
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08/30/2010
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Publication #:
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Pub Dt:
|
12/23/2010
| | | | |
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Title:
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TECHNIQUES FOR PROCESSOR/MEMORY CO-EXPLORATION AT MULTIPLE ABSTRACTION LEVELS
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