Patent Assignment Details
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| Reel/Frame: | 023634/0402 | |
| Pages: | 6 |
| | Recorded: | 12/08/2009 | | |
| Attorney Dkt #: | GET2CHIP |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09574572
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Filing Dt:
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05/17/2000
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Title:
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METHOD FOR TIMING ANALYSIS DURING AUTOMATIC SCHEDULING OF OPERATIONS IN THE HIGH-LEVEL SYNTHESIS OF DIGITAL SYSTEMS
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09574693
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Filing Dt:
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05/17/2000
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Title:
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METHOD FOR DELAY-OPTIMIZING TECHNOLOGY MAPPING OF DIGITAL LOGIC
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Assignee
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| 2655 SEELY AVENUE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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CADENCE DESIGN SYSTEMS, INC.
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2655 SEELY AVENUE
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SAN JOSE, CA 95134
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