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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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09203700
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Filing Dt:
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12/02/1998
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Title:
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CURRENT LIMITED, THERMALLY PROTECTED, POWER DEVICE
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09204904
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Filing Dt:
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12/03/1998
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Title:
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SEMICONDUCTOR PACKAGING METHOD
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09208457
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Filing Dt:
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12/10/1998
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Title:
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APPARATUS AND METHOD FOR TESTING SUBSCRIBER LOOP INTERFACE CIRCUITS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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09220780
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Filing Dt:
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12/24/1998
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Title:
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DC-TO-DC CONVERTER WITH INDUCTOR CURRENT SENSING AND RELATED METHODS
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09231184
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Filing Dt:
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01/14/1999
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Title:
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WIRELESS LOCAL AREA NETWORK SPREAD SPECTRUM TRANSCEIVER WITH MULTIPATH MITIGATION
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09231228
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Filing Dt:
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01/14/1999
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Title:
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SPREAD SPECTRUM TRANSCEIVER FOR USE IN WIRELESS LOCAL AREA NETWORK AND HAVING MULTIPATH MITIGATION
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09231608
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Filing Dt:
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01/14/1999
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Title:
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METHOD OF PERFORMING ANTENNA DIVERSITY IN SPREAD SPECTRUM IN WIRELESS LOCAL AREA NETWORK
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09246815
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Filing Dt:
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02/09/1999
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Title:
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FREQUENCY DEPENDENT RESISTIVE ELEMENT
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09247510
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Filing Dt:
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02/10/1999
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Title:
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COMPLEMENTARY MULTIPLEXER WITH LOW DISABLED-OUTPUT CAPACITANCE, AND METHOD
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09255231
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Filing Dt:
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02/22/1999
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Title:
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METHOD FOR FORMING A BONDED SUBSTRATE CONTAINING A PLANAR INTRINSIC GETTERING ZONE AND SUBSTRATE FORMED BY SAID METHOD
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09260411
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Filing Dt:
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03/01/1999
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Title:
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MOS-GATED DEVICE HAVING A BURIED GATE AND PROCESS FOR FORMING SAME
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09261981
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Filing Dt:
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03/04/1999
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Title:
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FEEDBACK-CONTROLLED LOW VOLTAGE CURRENT SINK/SOURCE
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09266066
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Filing Dt:
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03/10/1999
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Title:
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INTEGRATED CIRCUIT WITH DEEP TRENCH HAVING MULTIPLE SLOPES
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09268605
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Filing Dt:
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03/15/1999
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Title:
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METHOD FOR FABRICATING ELECTROSTATIC DISCHARGE PROTECTION DEVICE
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Patent #:
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04/02/2002
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Application #:
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09283530
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Filing Dt:
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04/01/1999
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Publication #:
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Pub Dt:
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11/29/2001
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Title:
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WAFER TRENCH ARTICLE AND PROCESS
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09283531
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Filing Dt:
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04/01/1999
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Title:
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HIGH DENSITY MOS-GATED POWER DEVICE AND PROCESS FOR FORMING SAME
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Patent #:
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NONE
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Application #:
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09283536
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Filing Dt:
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04/01/1999
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Publication #:
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Pub Dt:
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05/24/2001
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Title:
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POWER TRENCH MOS-GATED DEVICE AND PROCESS FOR FORMING SAME
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09303270
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Filing Dt:
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04/30/1999
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Title:
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POWER MOS DEVICE WITH INCREASED CHANNEL WIDTH AND PROCESS FOR FORMING SAME
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09307879
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Filing Dt:
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05/10/1999
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Title:
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PROCESS FOR FORMING MOS-GATED DEVICES HAVING SELF-ALIGNED TRENCHES
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Patent #:
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Issue Dt:
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01/01/2002
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Application #:
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09307896
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Filing Dt:
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05/10/1999
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Title:
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LASER DECAPSULATION METHOD
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09314323
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Filing Dt:
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05/19/1999
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Title:
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MOS-GATED POWER DEVICE HAVING EXTENDED TRENCH AND DOPING ZONE AND PROCESS FOR FORMING SAME
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Patent #:
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Issue Dt:
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06/21/2005
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Application #:
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09316580
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Filing Dt:
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05/21/1999
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Title:
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BONDED WAFER WITH METAL SILICIDATION
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09318334
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Filing Dt:
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05/25/1999
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Title:
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TRENCH-GATED DEVICE HAVING TRENCH WALLS FORMED BY SELECTIVE EPITAXIAL GROWTH AND PROCESS FOR FORMING DEVICE
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09324553
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Filing Dt:
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06/03/1999
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Title:
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LOW VOLTAGE DUAL-WELL MOS DEVICE HAVING HIGH RUGGEDNESS, LOW ON-RESISTANCE, AND IMPROVED BODY DIODE REVERSE RECOVERY
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09330437
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Filing Dt:
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06/11/1999
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Title:
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POWER DEVICE
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09334098
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Filing Dt:
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06/16/1999
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Title:
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POWER MODULE WITH LOWERED INDUCTANCE AND REDUCED VOLTAGE OVERSHOOTS
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09334835
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Filing Dt:
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06/17/1999
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Title:
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SELF-SUPPORTED ULTRATHIN SILICON WAFER PROCESS
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09334987
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Filing Dt:
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06/17/1999
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Title:
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DEFECT GETTERING BY INDUCED STRESS
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09334998
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Filing Dt:
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06/17/1999
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Title:
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CURRENT-CONTROLLED CARRIER TRACKING FILTER FOR IMPROVED SPURIOU SIGNAL SUPPRESSION
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Patent #:
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NONE
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Application #:
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09335113
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Filing Dt:
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06/17/1999
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SC-2 BASED PRE-THERMAL TREATMENT WAFER CLEANING PROCESS
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09338891
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Filing Dt:
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06/23/1999
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Title:
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SEMICONDUCTOR DEVICE GATE STRUCTURE FOR THERMAL OVERLOAD PROTECTION
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09339274
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Filing Dt:
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06/23/1999
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Title:
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METHOD OF FORMING AN INTEGRATED RESISTIVE CONTACTS WITH MOBILITY SPOILING IONS INCLUDING HIGH RESISTIVITY CONTACTS AND LOW RESISTIVITY SILICIDE CONTACTS
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09339356
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Filing Dt:
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06/24/1999
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Title:
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BACKMETAL DRAIN TERMINAL WITH LOW STRESS AND THERMAL RESISTANCE
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09342376
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06/29/1999
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Title:
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DUAL MODE CLASS D AMPLIFIERS
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Patent #:
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05/15/2001
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Application #:
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09342583
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Filing Dt:
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06/29/1999
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Title:
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RAKE RECEIVER WITH EMBEDDED DECISION FEEDBACK EQUALIZER
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09342948
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Filing Dt:
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06/29/1999
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Title:
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BRUSHLESS MULTIPASS SILICON WAFER CLEANING PROCESS FOR POST CHEMICAL MECHANICAL POLISHING USING IMMERSION
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Patent #:
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02/13/2007
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09343845
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06/30/1999
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Pub Dt:
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03/14/2002
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Title:
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METHOD OF MANUFACTURING A PLATED ELECTRONIC TERMINATION
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09344867
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06/28/1999
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Title:
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POTTED TRANSDUCER ARRAY WITH MATCHING NETWORK IN A MULTIPLE PASS CONFIGURATION
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Patent #:
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03/26/2002
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09345261
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06/30/1999
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Title:
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METHOD FOR MAKING A DIFFUSED BACK-SIDE LAYER ON A BONDED-WAFER WITH A THICK BOND OXIDE
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02/26/2002
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Application #:
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09345929
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07/01/1999
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Title:
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LOW TEMPERATURE COEFFICIENT RESISTOR (TCRL)
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Patent #:
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03/06/2001
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09345930
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07/01/1999
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Title:
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POWER SEMICONDUCTOR MOUNTING PACKAGE CONTAINING BALL GRID ARRAY
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09350575
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07/09/1999
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Title:
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PROCESS FOR FORMING VERTICAL SEMICONDUCTOR DEVICE HAVING INCREASED SOURCE CONTACT AREA
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Patent #:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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Patent #:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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