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Total properties:
14
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Patent #:
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Issue Dt:
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12/20/2011
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Application #:
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10387802
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Filing Dt:
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03/13/2003
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Title:
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AUTOMATED BOTTOM-UP AND TOP-DOWN PARTITIONED DESIGN SYNTHESIS
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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10626031
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Filing Dt:
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07/23/2003
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Publication #:
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Pub Dt:
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07/29/2004
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Title:
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INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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07/26/2011
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Application #:
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10956327
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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APPARATUS AND METHOD FOR LICENSING PROGRAMMABLE HARDWARE SUB-DESIGNS USING A HOST-IDENTIFIER
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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10958899
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Filing Dt:
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10/04/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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METHODS AND APPARATUSES FOR AUTOMATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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10993760
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Filing Dt:
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11/19/2004
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Title:
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METHODS AND APPARATUSES FOR CIRCUIT SIMULATION
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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11026277
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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09/01/2005
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Title:
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DESIGN INSTRUMENTATION CIRCUITRY
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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11124496
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Filing Dt:
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05/04/2005
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Title:
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METHODS AND APPARATUSES FOR AUTOMATED CIRCUIT OPTIMIZATION AND VERIFICATION
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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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11184294
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Filing Dt:
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07/18/2005
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Publication #:
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Pub Dt:
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11/17/2005
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Title:
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METHOD AND APPARATUS FOR RESETABLE MEMORY AND DESIGN APPROACH FOR SAME
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11195180
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Filing Dt:
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08/02/2005
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Publication #:
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Pub Dt:
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11/16/2006
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Title:
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METHOD AND SYSTEM FOR DEBUG AND TEST USING REPLICATED LOGIC
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11218400
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Filing Dt:
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09/01/2005
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Title:
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RESETTABLE MEMORY APPARATUSES AND DESIGN
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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11254196
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Filing Dt:
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10/18/2005
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Publication #:
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Pub Dt:
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03/09/2006
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Title:
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METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUITS (ICS) WITH OPTIMIZATION AT REGISTER TRANSFER LEVEL (RTL) AMONGST MULTIPLE ICS
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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11292616
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Filing Dt:
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12/01/2005
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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METHOD AND APPARATUS TO ESTIMATE DELAY FOR LOGIC CIRCUIT OPTIMIZATION
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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11305425
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Filing Dt:
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12/16/2005
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
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Title:
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METHODS AND APPARATUSES TO GENERATE A SHIELDING MESH FOR INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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11344316
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Filing Dt:
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01/30/2006
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Publication #:
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Pub Dt:
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09/07/2006
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Title:
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METHOD AND APPARATUS FOR THE DESIGN AND ANALYSIS OF DIGITAL CIRCUITS WITH TIME DIVISION MULTIPLEXING
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