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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:043095/0414   Pages: 6
Recorded: 07/25/2017
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14
1
Patent #:
Issue Dt:
09/07/2010
Application #:
10351590
Filing Dt:
01/27/2003
Publication #:
Pub Dt:
01/01/2004
Title:
DYNAMIC PHASE TRACKING USING EDGE DETECTION
2
Patent #:
Issue Dt:
12/20/2005
Application #:
10648090
Filing Dt:
08/26/2003
Title:
CLOCK SIGNAL GENERATORS HAVING PROGRAMMABLE FULL-PERIOD CLOCK SKEW CONTROL AND METHODS OF GENERATING CLOCK SIGNALS HAVING PROGRAMMABLE SKEWS
3
Patent #:
Issue Dt:
11/07/2006
Application #:
10686420
Filing Dt:
10/15/2003
Title:
DATA PATHS WITH RECEIVER TIMING FIXABLE TO A DOWNSTREAM STAGE AND METHODS OF OPERATION THEREOF
4
Patent #:
Issue Dt:
12/06/2005
Application #:
10774904
Filing Dt:
02/09/2004
Title:
DOUBLE DATA RATE MEMORY DEVICES INCLUDING CLOCK DOMAIN ALIGNMENT CIRCUITS AND METHODS OF OPERATION THEREOF
5
Patent #:
Issue Dt:
03/27/2007
Application #:
10979979
Filing Dt:
11/03/2004
Title:
PROGRAMMABLE CLOCK DRIVERS THAT SUPPORT CRC ERROR CHECKING OF CONFIGURATION DATA DURING PROGRAM RESTORE OPERATIONS
6
Patent #:
Issue Dt:
09/11/2007
Application #:
11050009
Filing Dt:
02/02/2005
Title:
METHOD AND APPARATUS FOR BUFFER WITH PROGRAMMABLE SKEW
7
Patent #:
Issue Dt:
03/24/2009
Application #:
11092032
Filing Dt:
03/29/2005
Title:
INTEGRATED CIRCUITS AND METHODS WITH STATISTICS-BASED INPUT DATA SIGNAL SAMPLE TIMING
8
Patent #:
Issue Dt:
12/19/2006
Application #:
11217195
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
02/23/2006
Title:
CLOCK SIGNAL GENERATORS HAVING PROGRAMMABLE FULL-PERIOD CLOCK SKEW CONTROL
9
Patent #:
Issue Dt:
09/25/2007
Application #:
11229472
Filing Dt:
09/15/2005
Title:
LOW JITTER FREQUENCY SYNTHESIZER
10
Patent #:
Issue Dt:
06/09/2009
Application #:
11462627
Filing Dt:
08/04/2006
Title:
MULTIPHASE CLOCK GENERATOR
11
Patent #:
Issue Dt:
12/27/2011
Application #:
12338970
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
06/25/2009
Title:
OVERCLOCKING WITH PHASE SELECTION
12
Patent #:
Issue Dt:
01/10/2012
Application #:
12845434
Filing Dt:
07/28/2010
Publication #:
Pub Dt:
11/25/2010
Title:
Dynamic phase tracking using edge detection that employs an edge counter
13
Patent #:
Issue Dt:
09/03/2019
Application #:
15605408
Filing Dt:
05/25/2017
Publication #:
Pub Dt:
11/30/2017
Title:
REGISTER CLOCK DRIVER FOR DDR5 MEMORY
14
Patent #:
NONE
Issue Dt:
Application #:
15616553
Filing Dt:
06/07/2017
Publication #:
Pub Dt:
12/14/2017
Title:
AUTONOMOUS POWER AND TIMING SYSTEM
Assignor
1
Exec Dt:
06/28/2017
Assignee
1
270 PARK AVENUE
NEW YORK, NEW YORK 10017
Correspondence name and address
RICHARD SWOPE
6024 SILVER CREEK VALLEY ROAD
SAN JOSE, CA 95138

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