Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 020171/0427 | |
| Pages: | 3 |
| | Recorded: | 11/28/2007 | | |
Attorney Dkt #: | 07-480- C AND 07-480-D |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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11614241
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Filing Dt:
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12/21/2006
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Publication #:
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Pub Dt:
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05/10/2007
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Title:
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STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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11614252
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Filing Dt:
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12/21/2006
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Publication #:
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Pub Dt:
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05/03/2007
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Title:
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STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER
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Assignee
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3080 OLCOTT DRIVE, SUITE 215-D |
SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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ROBERT J. IRVINE
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300 SOUTH WACKER SUITE 3100
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CHICAGO, IL 60606-6709
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