USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	035308/0428			Pages:	83
		Recorded:	03/24/2015
Attorney Dkt #:	40767-149
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 100
Page 1 of 2
Pages: 1 2

1

Patent #:	6489835	Issue Dt:	12/03/2002	Application #:	09941454	Filing Dt:	08/28/2001
Title:	LOW VOLTAGE BANDGAP REFERENCE CIRCUIT

2

Patent #:	6593222	Issue Dt:	07/15/2003	Application #:	09949112	Filing Dt:	09/07/2001
Publication #:	US20030049923	Pub Dt:	03/13/2003
Title:	METHOD TO IMPROVE THE RELIABILITY OF THERMOSONIC GOLD TO ALUMINUM WIRE BONDS

3

Patent #:	6832231	Issue Dt:	12/14/2004	Application #:	09966967	Filing Dt:	09/28/2001
Title:	MULTIPLE WIDTH RANDOM NUMBER GENERATION

4

Patent #:	6611463	Issue Dt:	08/26/2003	Application #:	09991245	Filing Dt:	11/14/2001
Title:	ZERO-POWER PROGRAMMABLE MEMORY CELL

5

Patent #:	6489806	Issue Dt:	12/03/2002	Application #:	09992493	Filing Dt:	11/14/2001
Title:	ZERO-POWER LOGIC CELL FOR USE IN PROGRAMMABLE LOGIC DEVICES

6

Patent #:	6993108	Issue Dt:	01/31/2006	Application #:	10006516	Filing Dt:	12/03/2001
Title:	DIGITAL PHASE LOCKED LOOP WITH PROGRAMMABLE DIGITAL FILTER

7

Patent #:	7003066	Issue Dt:	02/21/2006	Application #:	10006559	Filing Dt:	12/03/2001
Title:	DIGITAL PHASE LOCKED LOOP WITH PHASE SELECTOR HAVING MINIMIZED NUMBER OF PHASE INTERPOLATORS

8

Patent #:	6999543	Issue Dt:	02/14/2006	Application #:	10006610	Filing Dt:	12/03/2001
Title:	CLOCK DATA RECOVERY DESERIALIZER WITH PROGRAMMABLE SYNC DETECT LOGIC

9

Patent #:	6515899	Issue Dt:	02/04/2003	Application #:	10010011	Filing Dt:	11/09/2001
Title:	NON-VOLATILE MEMORY CELL WITH ENHANCED CELL DRIVE CURRENT

10

Patent #:	6693830	Issue Dt:	02/17/2004	Application #:	10011549	Filing Dt:	10/22/2001
Title:	SINGLE-POLY TWO-TRANSISTOR EEPROM CELL WITH DIFFERENTIALLY DOPED FLOATING GATE

11

Patent #:	6636422	Issue Dt:	10/21/2003	Application #:	10014905	Filing Dt:	12/11/2001
Title:	DATA STORAGE SYSTEMS WITH ENHANCED COOLING

12

Patent #:	6674303	Issue Dt:	01/06/2004	Application #:	10017725	Filing Dt:	12/14/2001
Title:	PROGRAMMABLE INPUT/OUTPUT CELL WITH BIDIRECTIONAL AND SHIFT REGISTER CAPABILITIES

13

Patent #:	6605959	Issue Dt:	08/12/2003	Application #:	10017859	Filing Dt:	12/14/2001
Title:	STRUCTURE AND METHOD FOR IMPLEMENTING WIDE MULTIPLEXERS

14

Patent #:	6703860	Issue Dt:	03/09/2004	Application #:	10021844	Filing Dt:	12/14/2001
Title:	I/O BLOCK FOR A PROGRAMMABLE INTERCONNECT CIRCUIT

15

Patent #:	6661254	Issue Dt:	12/09/2003	Application #:	10021873	Filing Dt:	12/14/2001
Title:	PROGRAMMABLE INTERCONNECT CIRCUIT WITH A PHASE-LOCKED LOOP

16

Patent #:	7154298	Issue Dt:	12/26/2006	Application #:	10022464	Filing Dt:	12/14/2001
Title:	BLOCK-ORIENTED ARCHITECTURE FOR A PROGRAMMABLE INTERCONNECT CIRCUIT

17

Patent #:	6653861	Issue Dt:	11/25/2003	Application #:	10023053	Filing Dt:	12/14/2001
Title:	MULTI-LEVEL ROUTING STRUCTURE FOR A PROGRAMMABLE INTERCONNECT CIRCUIT

18

Patent #:	6650141	Issue Dt:	11/18/2003	Application #:	10023226	Filing Dt:	12/14/2001
Publication #:	US20030112031	Pub Dt:	06/19/2003
Title:	HIGH SPEED INTERFACE FOR A PROGRAMMABLE INTERCONNECT CIRCUIT

19

Patent #:	6989551	Issue Dt:	01/24/2006	Application #:	10053004	Filing Dt:	11/02/2001
Publication #:	US20030085727	Pub Dt:	05/08/2003
Title:	Test structure for determining a minimum tunnel opening size in a non-volatile memory

20

Patent #:	6845044	Issue Dt:	01/18/2005	Application #:	10061057	Filing Dt:	01/29/2002
Publication #:	US20030143793	Pub Dt:	07/31/2003
Title:	METHOD OF PREVENTING HIGH ICC AT START-UP IN ZERO-POWER EEPROM CELLS FOR PLD APPLICATIONS

21

Patent #:	6680625	Issue Dt:	01/20/2004	Application #:	10066031	Filing Dt:	01/31/2002
Title:	SYMMETRICAL CML LOGIC GATE SYSTEM

22

Patent #:	6781170	Issue Dt:	08/24/2004	Application #:	10082050	Filing Dt:	02/14/2002
Publication #:	US20020163048	Pub Dt:	11/07/2002
Title:	INTEGRATED CIRCUIT BASE TRANSISTOR STRUCTURE AND ASSOCIATED PROGRAMMABLE CELL LIBRARY

23

Patent #:	6600188	Issue Dt:	07/29/2003	Application #:	10083728	Filing Dt:	02/26/2002
Title:	EEPROM WITH A NEUTRALIZED DOPING AT TUNNEL WINDOW EDGE

24

Patent #:	6621298	Issue Dt:	09/16/2003	Application #:	10090209	Filing Dt:	03/04/2002
Publication #:	US20020186044	Pub Dt:	12/12/2002
Title:	VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS

25

Patent #:	6795959	Issue Dt:	09/21/2004	Application #:	10103100	Filing Dt:	03/21/2002
Title:	INTEGRATED DELAY DISCRIMINATOR FOR USE WITH A FIELD-PROGRAMMABLE GATE ARRAY AND A METHOD OF DETERMINING A TIME DELAY THEREOF

26

Patent #:	6907439	Issue Dt:	06/14/2005	Application #:	10106509	Filing Dt:	03/26/2002
Title:	FFT ADDRESS GENERATION METHOD AND APPARATUS

27

Patent #:	6976047	Issue Dt:	12/13/2005	Application #:	10108401	Filing Dt:	03/28/2002
Title:	SKIPPED CARRY INCREMENTER FOR FFT ADDRESS GENERATION

28

Patent #:	6639431	Issue Dt:	10/28/2003	Application #:	10112370	Filing Dt:	03/29/2002
Title:	DIFFERENTIAL INPUT COMPARATOR

29

Patent #:	6660579	Issue Dt:	12/09/2003	Application #:	10128943	Filing Dt:	04/24/2002
Title:	ZERO POWER MEMORY CELL WITH IMPROVED DATA RETENTION

30

Patent #:	7032162	Issue Dt:	04/18/2006	Application #:	10131883	Filing Dt:	04/25/2002
Title:	POLYNOMIAL EXPANDER FOR GENERATING COEFFICIENTS OF A POLYNOMIAL FROM ROOTS OF THE POLYNOMIAL

31

Patent #:	6765408	Issue Dt:	07/20/2004	Application #:	10133106	Filing Dt:	04/26/2002
Publication #:	US20040000928	Pub Dt:	01/01/2004
Title:	DEVICE AND METHOD WITH GENERIC LOGIC BLOCKS

32

Patent #:	6814296	Issue Dt:	11/09/2004	Application #:	10135308	Filing Dt:	04/30/2002
Publication #:	US20020167042	Pub Dt:	11/14/2002
Title:	INTEGRATED CIRCUIT AND ASSOCIATED DESIGN METHOD WITH ANTENNA ERROR CONTROL USING SPARE GATES

33

Patent #:	6600341	Issue Dt:	07/29/2003	Application #:	10135325	Filing Dt:	04/30/2002
Publication #:	US20020163354	Pub Dt:	11/07/2002
Title:	INTEGRATED CIRCUIT AND ASSOCIATED DESIGN METHOD USING SPARE GATE ISLANDS

34

Patent #:	6720755	Issue Dt:	04/13/2004	Application #:	10146734	Filing Dt:	05/16/2002
Title:	BAND GAP REFERENCE CIRCUIT

35

Patent #:	6714048	Issue Dt:	03/30/2004	Application #:	10146739	Filing Dt:	05/16/2002
Title:	INPUT BUFFER WITH SELECTABLE PCL, GTL, OR PECL COMPATIBILITY

36

Patent #:	6870391	Issue Dt:	03/22/2005	Application #:	10146769	Filing Dt:	05/16/2002
Title:	INPUT BUFFER WITH CMOS DRIVER GATE CURRENT CONTROL ENABLING SELECTABLE PCL, GTL, OR PECL COMPATIBILITY

37

Patent #:	6657458	Issue Dt:	12/02/2003	Application #:	10146826	Filing Dt:	05/16/2002
Title:	OUTPUT BUFFER WITH FEEDBACK FROM AN INPUT BUFFER TO PROVIDE SELECTABLE PCL, GTL OR PECL COMPATIBILITY

38

Patent #:	6760209	Issue Dt:	07/06/2004	Application #:	10147011	Filing Dt:	05/16/2002
Title:	ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

39

Patent #:	6714043	Issue Dt:	03/30/2004	Application #:	10147199	Filing Dt:	05/16/2002
Title:	OUTPUT BUFFER HAVING PROGRAMMABLE DRIVE CURRENT AND OUTPUT VOLTAGE LIMITS

40

Patent #:	6848095	Issue Dt:	01/25/2005	Application #:	10150410	Filing Dt:	05/17/2002
Title:	METHOD OF ASSIGNING LOGIC FUNCTIONS TO MACROCELLS IN A PROGRAMMABLE LOGIC DEVICE

41

Patent #:	6798244	Issue Dt:	09/28/2004	Application #:	10151753	Filing Dt:	05/16/2002
Title:	OUTPUT BUFFER WITH OVERVOLTAGE PROTECTION

42

Patent #:	6583652	Issue Dt:	06/24/2003	Application #:	10159009	Filing Dt:	05/30/2002
Title:	HIGHLY LINEAR PROGRAMMABLE TRANSCONDUCTOR WITH LARGE INPUT-SIGNAL RANGE

43

Patent #:	6717451	Issue Dt:	04/06/2004	Application #:	10159089	Filing Dt:	05/30/2002
Title:	PRECISION ANALOG LEVEL SHIFTER WITH PROGRAMMABLE OPTIONS

44

Patent #:	6806771	Issue Dt:	10/19/2004	Application #:	10159681	Filing Dt:	05/31/2002
Title:	MULTIMODE OUTPUT STAGE CONVERTING DIFFERENTIAL TO SINGLE-ENDED SIGNALS USING CURRENT-MODE INPUT SIGNALS

45

Patent #:	6794236	Issue Dt:	09/21/2004	Application #:	10160855	Filing Dt:	06/03/2002
Title:	EEPROM DEVICE WITH IMPROVED CAPACITIVE COUPLING AND FABRICATION PROCESS

46

Patent #:	6716705	Issue Dt:	04/06/2004	Application #:	10161283	Filing Dt:	06/03/2002
Title:	EEPROM DEVICE HAVING A RETROGRADE PROGRAM JUNCTION REGION AND PROCESS FOR FABRICATING THE DEVICE

47

Patent #:	6596587	Issue Dt:	07/22/2003	Application #:	10162337	Filing Dt:	06/03/2002
Title:	SHALLOW JUNCTION EEPROM DEVICE AND PROCESS FOR FABRICATING THE DEVICE

48

Patent #:	6703305	Issue Dt:	03/09/2004	Application #:	10164484	Filing Dt:	06/05/2002
Title:	SEMICONDUCTOR DEVICE HAVING METALLIZED INTERCONNECT STRUCTURE AND METHOD OF FABRICATION

49

Patent #:	6844757	Issue Dt:	01/18/2005	Application #:	10187236	Filing Dt:	06/28/2002
Publication #:	US20040000927	Pub Dt:	01/01/2004
Title:	CONVERTING BITS TO VECTORS IN A PROGRAMMABLE LOGIC DEVICE

50

Patent #:	6650143	Issue Dt:	11/18/2003	Application #:	10191888	Filing Dt:	07/08/2002
Title:	FIELD PROGRAMMABLE GATE ARRAY BASED UPON TRANSISTOR GATE OXIDE BREAKDOWN

51

Patent #:	7028281	Issue Dt:	04/11/2006	Application #:	10194771	Filing Dt:	07/12/2002
Title:	FPGA WITH REGISTER-INTENSIVE ARCHITECTURE

52

Patent #:	6714066	Issue Dt:	03/30/2004	Application #:	10200645	Filing Dt:	07/22/2002
Publication #:	US20020186074	Pub Dt:	12/12/2002
Title:	INTEGRATED PROGRAMMABLE CONTINUOUS TIME FILTER WITH PROGRAMMABLE CAPACITOR ARRAYS

53

Patent #:	6683477	Issue Dt:	01/27/2004	Application #:	10207292	Filing Dt:	07/29/2002
Title:	MEMORY CELL

54

Patent #:	6938197	Issue Dt:	08/30/2005	Application #:	10210367	Filing Dt:	08/01/2002
Publication #:	US20040025105	Pub Dt:	02/05/2004
Title:	CRC CALCULATION SYSTEM AND METHOD FOR A PACKET ARRIVING ON AN N-BYTE WIDE BUS

55

Patent #:	6545313	Issue Dt:	04/08/2003	Application #:	10211125	Filing Dt:	08/02/2002
Title:	EEPROM TUNNEL WINDOW FOR PROGRAM INJECTION VIA P+ CONTACTED INVERSION

56

Patent #:	6650142	Issue Dt:	11/18/2003	Application #:	10219046	Filing Dt:	08/13/2002
Title:	ENHANCED CPLD MACROCELL MODULE HAVING SELECTABLE BYPASS OF STEERING-BASED RESOURCE ALLOCATION AND METHODS OF USE

57

Patent #:	6841447	Issue Dt:	01/11/2005	Application #:	10232912	Filing Dt:	08/30/2002
Title:	EEPROM DEVICE HAVING AN ISOLATION-BOUNDED TUNNEL CAPACITOR AND FABRICATION PROCESS

58

Patent #:	7043511	Issue Dt:	05/09/2006	Application #:	10233021	Filing Dt:	08/30/2002
Title:	PERFORMING CONDITIONAL OPERATIONS IN A PROGRAMMABLE LOGIC DEVICE

59

Patent #:	6725442	Issue Dt:	04/20/2004	Application #:	10235380	Filing Dt:	09/04/2002
Title:	SCALABLE AND PARALLEL PROCESSING METHODS AND STRUCTURES FOR TESTING CONFIGURABLE INTERCONNECT NETWORK IN FPGA DEVICE

60

Patent #:	6833602	Issue Dt:	12/21/2004	Application #:	10236114	Filing Dt:	09/06/2002
Title:	DEVICE HAVING ELECTICALLY ISOLATED LOW VOLTAGE AND HIGH VOLTAGE REGIONS AND PROCESS FOR FABRICATING THE DEVICE

61

Patent #:	6649514	Issue Dt:	11/18/2003	Application #:	10236718	Filing Dt:	09/06/2002
Title:	EEPROM DEVICE HAVING IMPROVED DATA RETENTION AND PROCESS FOR FABRICATING THE DEVICE

62

Patent #:	6842372	Issue Dt:	01/11/2005	Application #:	10236829	Filing Dt:	09/06/2002
Title:	EEPROM CELL HAVING A FLOATING-GATE TRANSISTOR WITHIN A CELL WELL AND A PROCESS FOR FABRICATING THE MEMORY CELL

63

Patent #:	6738306	Issue Dt:	05/18/2004	Application #:	10242809	Filing Dt:	09/13/2002
Publication #:	US20040052147	Pub Dt:	03/18/2004
Title:	SRAM CELL WITH SINGLE-ENDED AND DIFFERENTIAL READ/WRITE PORTS

64

Patent #:	6917536	Issue Dt:	07/12/2005	Application #:	10243014	Filing Dt:	09/13/2002
Title:	MEMORY ACCESS CIRCUIT AND METHOD FOR READING AND WRITING DATA WITH THE SAME CLOCK SIGNAL

65

Patent #:	6700154	Issue Dt:	03/02/2004	Application #:	10251608	Filing Dt:	09/20/2002
Title:	EEPROM CELL WITH TRENCH COUPLING CAPACITOR

66

Patent #:	6907592	Issue Dt:	06/14/2005	Application #:	10255474	Filing Dt:	09/25/2002
Title:	METHOD OF ROUTING IN A PROGRAMMABLE LOGIC DEVICE

67

Patent #:	6803787	Issue Dt:	10/12/2004	Application #:	10255499	Filing Dt:	09/25/2002
Title:	STATE MACHINE IN A PROGRAMMABLE LOGIC DEVICE

68

Patent #:	6812738	Issue Dt:	11/02/2004	Application #:	10255656	Filing Dt:	09/25/2002
Title:	VECTOR ROUTING IN A PROGRAMMABLE LOGIC DEVICE

69

Patent #:	6809551	Issue Dt:	10/26/2004	Application #:	10255875	Filing Dt:	09/25/2002
Title:	METHOD OF OPTIMIZING ROUTING IN A PROGRAMMABLE LOGIC DEVICE

70

Patent #:	6748575	Issue Dt:	06/08/2004	Application #:	10263251	Filing Dt:	10/02/2002
Title:	PROGRAMMING PROGRAMMABLE LOGIC DEVICES USING HIDDEN SWITCHES

71

Patent #:	6846714	Issue Dt:	01/25/2005	Application #:	10263507	Filing Dt:	10/03/2002
Title:	VOLTAGE LIMITED EEPROM DEVICE AND PROCESS FOR FABRICATING THE DEVICE

72

Patent #:	6639434	Issue Dt:	10/28/2003	Application #:	10266361	Filing Dt:	10/07/2002
Title:	LOW VOLTAGE DIFFERENTIAL SIGNALING SYSTEMS AND METHODS

73

Patent #:	6762618	Issue Dt:	07/13/2004	Application #:	10269439	Filing Dt:	10/11/2002
Title:	VERIFY SCHEME FOR A MULTI-LEVEL ROUTING STRUCTURE

74

Patent #:	6791394	Issue Dt:	09/14/2004	Application #:	10269450	Filing Dt:	10/10/2002
Publication #:	US20040070998	Pub Dt:	04/15/2004
Title:	POWER SUPPLY CONTROL CIRCUITS

75

Patent #:	7111183	Issue Dt:	09/19/2006	Application #:	10269804	Filing Dt:	10/10/2002
Title:	EXPANSION METHOD FOR COMPLEX POWER-SEQUENCING APPLICATIONS

76

Patent #:	6901572	Issue Dt:	05/31/2005	Application #:	10272582	Filing Dt:	10/15/2002
Title:	POWER SEQUENCE CONTROLLER PROGRAMMING TECHNIQUE

77

Patent #:	6639449	Issue Dt:	10/28/2003	Application #:	10278415	Filing Dt:	10/22/2002
Title:	ASYNCHRONOUS GLITCH-FREE CLOCK MULTIPLEXER

78

Patent #:	7051261	Issue Dt:	05/23/2006	Application #:	10282524	Filing Dt:	10/29/2002
Title:	TURBO ENCODER WITH REDUCED PROCESSING DELAY

79

Patent #:	6700823	Issue Dt:	03/02/2004	Application #:	10283765	Filing Dt:	10/30/2002
Title:	PROGRAMMABLE COMMON MODE TERMINATION FOR INPUT/OUTPUT CIRCUITS

80

Patent #:	7000210	Issue Dt:	02/14/2006	Application #:	10288667	Filing Dt:	11/05/2002
Publication #:	US20040088671	Pub Dt:	05/06/2004
Title:	ADAPTIVE ADJUSTMENT OF CONSTRAINTS DURING PLD PLACEMENT PROCESSING

81

Patent #:	6813754	Issue Dt:	11/02/2004	Application #:	10288668	Filing Dt:	11/05/2002
Publication #:	US20040088663	Pub Dt:	05/06/2004
Title:	PLACEMENT PROCESSING FOR PROGRAMMABLE LOGIC DEVICES

82

Patent #:	6825733	Issue Dt:	11/30/2004	Application #:	10300190	Filing Dt:	11/20/2002
Title:	LOW JITTER INTEGRATED PHASE LOCKED LOOP WITH BROAD TUNING RANGE

83

Patent #:	6797568	Issue Dt:	09/28/2004	Application #:	10302439	Filing Dt:	11/21/2002
Title:	FLASH TECHNOLOGY TRANSISTORS AND METHODS FOR FORMING THE SAME

84

Patent #:	6710641	Issue Dt:	03/23/2004	Application #:	10308420	Filing Dt:	12/02/2002
Title:	BANDGAP REFERENCE CIRCUIT FOR IMPROVED START-UP

85

Patent #:	6650188	Issue Dt:	11/18/2003	Application #:	10309302	Filing Dt:	12/02/2002
Title:	COUPLING FOR LC-BASED VCO

86

Patent #:	6777979	Issue Dt:	08/17/2004	Application #:	10334642	Filing Dt:	12/31/2002
Title:	FIFO MEMORY ARCHITECTURE

87

Patent #:	6753696	Issue Dt:	06/22/2004	Application #:	10338619	Filing Dt:	01/08/2003
Title:	PROGRAMMABLE OPTIMIZED-DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD

88

Patent #:	7034596	Issue Dt:	04/25/2006	Application #:	10365083	Filing Dt:	02/11/2003
Publication #:	US20040155690	Pub Dt:	08/12/2004
Title:	ADAPTIVE INPUT LOGIC FOR PHASE ADJUSTMENTS

89

Patent #:	6788101	Issue Dt:	09/07/2004	Application #:	10366956	Filing Dt:	02/13/2003
Publication #:	US20040160242	Pub Dt:	08/19/2004
Title:	PROGRAMMABLE INTERFACE CIRCUIT FOR DIFFERENTIAL AND SINGLE-ENDED SIGNALS

90

Patent #:	6812869	Issue Dt:	11/02/2004	Application #:	10367323	Filing Dt:	02/13/2003
Title:	NOISE REDUCTION TECHNIQUES FOR PROGRAMMABLE INPUT/OUTPUT CIRCUITS

91

Patent #:	6915323	Issue Dt:	07/05/2005	Application #:	10368023	Filing Dt:	02/13/2003
Title:	MACROCELLS SUPPORTING A CARRY CASCADE

92

Patent #:	6861870	Issue Dt:	03/01/2005	Application #:	10370232	Filing Dt:	02/19/2003
Title:	DYNAMIC CROSS POINT SWITCH WITH SHADOW MEMORY ARCHITECTURE

93

Patent #:	6859066	Issue Dt:	02/22/2005	Application #:	10377320	Filing Dt:	02/28/2003
Title:	BANK-BASED INPUT/OUTPUT BUFFERS WITH MULTIPLE REFERENCE VOLTAGES

94

Patent #:	7339952	Issue Dt:	03/04/2008	Application #:	10387243	Filing Dt:	03/12/2003
Title:	POINTER PROCESSING FOR OPTICAL COMMUNICATION SYSTEMS

95

Patent #:	7305047	Issue Dt:	12/04/2007	Application #:	10387814	Filing Dt:	03/12/2003
Title:	AUTOMATIC LANE ASSIGNMENT FOR A RECEIVER

96

Patent #:	6870395	Issue Dt:	03/22/2005	Application #:	10391094	Filing Dt:	03/18/2003
Publication #:	US20040183564	Pub Dt:	09/23/2004
Title:	PROGRAMMABLE LOGIC DEVICES WITH INTEGRATED STANDARD-CELL LOGIC BLOCKS

97

Patent #:	RE39510	Issue Dt:	03/13/2007	Application #:	10392751	Filing Dt:	03/20/2003
Title:	FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS WITH REGISTERED ADDRESS AND DATA INPUT SECTIONS

98

Patent #:	6967500	Issue Dt:	11/22/2005	Application #:	10397669	Filing Dt:	03/26/2003
Title:	ELECTRONIC CIRCUIT WITH ON-CHIP PROGRAMMABLE TERMINATIONS

99

Patent #:	6873187	Issue Dt:	03/29/2005	Application #:	10400705	Filing Dt:	03/27/2003
Title:	METHOD AND APPARATUS FOR CONTROLLING SIGNAL DISTRIBUTION IN AN ELECTRONIC CIRCUIT

100

Patent #:	7000212	Issue Dt:	02/14/2006	Application #:	10406050	Filing Dt:	04/02/2003
Publication #:	US20040010767	Pub Dt:	01/15/2004
Title:	HIERARCHICAL GENERAL INTERCONNECT ARCHITECTURE FOR HIGH DENSITY FPGA'S

Assignors

1

LATTICE SEMICONDUCTOR CORPORATION

Exec Dt:

03/10/2015

2

Exec Dt:

03/10/2015

3

SILICON IMAGE, INC.

Exec Dt:

03/10/2015

4

Exec Dt:

03/10/2015

Assignee

1

JEFFERIES FINANCE LLC

520 MADISON AVENUE

NEW YORK, NEW YORK 10022

Correspondence name and address
	PROSKAUER ROSE LLP
	ONE INTERNATIONAL PLACE
	BOSTON, MA 02110

Search Results as of: 05/24/2024 04:53 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6

| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT