Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 064652/0438 | |
| Pages: | 17 |
| | Recorded: | 08/21/2023 | | |
| Attorney Dkt #: | 1535-707 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/18/2024
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Application #:
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17694657
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Filing Dt:
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03/14/2022
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Publication #:
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Pub Dt:
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11/24/2022
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Title:
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LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC)
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Assignee
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| 129, SAMSUNG-RO, YEONGTONG-GU |
| SUWON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF 16677 |
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Correspondence name and address
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RENAISSANCE IP LAW GROUP LLP (PIP)
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17933 NW EVERGREEN PLACE, SUITE 121
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BEAVERTON, OR 97006
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06/14/2024 09:47 AM
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