Total properties:
31
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Patent #:
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Issue Dt:
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10/13/2015
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Application #:
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14187708
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Filing Dt:
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02/24/2014
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Publication #:
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Pub Dt:
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08/27/2015
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Title:
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III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
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04/26/2016
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Application #:
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14793772
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Filing Dt:
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07/08/2015
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Publication #:
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Pub Dt:
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11/12/2015
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Title:
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III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
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01/01/2019
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Application #:
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15157012
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Filing Dt:
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05/17/2016
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Publication #:
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Pub Dt:
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11/23/2017
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Title:
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VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT
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Patent #:
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Issue Dt:
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01/02/2018
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Application #:
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15177941
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Filing Dt:
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06/09/2016
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Publication #:
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Pub Dt:
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12/14/2017
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Title:
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METHODS FOR FORMING HYBRID VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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10/10/2017
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Application #:
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15180251
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Filing Dt:
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06/13/2016
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Title:
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VERTICAL SCHOTTKY BARRIER FET
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Patent #:
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Issue Dt:
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02/27/2018
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Application #:
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15191566
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Filing Dt:
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06/24/2016
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Publication #:
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Pub Dt:
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12/28/2017
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Title:
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FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
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Patent #:
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Issue Dt:
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02/26/2019
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Application #:
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15195498
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Filing Dt:
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06/28/2016
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Publication #:
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Pub Dt:
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12/28/2017
| | | | |
Title:
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FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AN ASYMMETRIC GATE STRUCTURE
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Patent #:
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Issue Dt:
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08/29/2017
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Application #:
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15216383
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Filing Dt:
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07/21/2016
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Title:
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METHOD FOR FORMING VERTICAL SCHOTTKY CONTACT FET
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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15243491
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Filing Dt:
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08/22/2016
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Publication #:
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Pub Dt:
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02/22/2018
| | | | |
Title:
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VERTICAL ANTIFUSE STRUCTURES
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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15247267
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Filing Dt:
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08/25/2016
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Publication #:
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Pub Dt:
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03/01/2018
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Title:
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VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE
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Patent #:
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Issue Dt:
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07/11/2017
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Application #:
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15269180
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Filing Dt:
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09/19/2016
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Title:
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VERTICAL FET WITH STRAINED CHANNEL
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Patent #:
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Issue Dt:
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06/19/2018
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Application #:
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15282272
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Filing Dt:
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09/30/2016
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Publication #:
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Pub Dt:
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04/05/2018
| | | | |
Title:
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VERTICAL FIN RESISTOR DEVICES
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Patent #:
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Issue Dt:
|
07/25/2017
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Application #:
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15282398
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Filing Dt:
|
09/30/2016
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Title:
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REDUCED CAPACITANCE IN VERTICAL TRANSISTORS BY PREVENTING EXCESSIVE OVERLAP BETWEEN THE GATE AND THE SOURCE/DRAIN
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Patent #:
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|
Issue Dt:
|
05/09/2017
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Application #:
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15297377
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Filing Dt:
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10/19/2016
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Title:
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VERTICAL FET SYMMETRIC AND ASYMMETRIC SOURCE/DRAIN FORMATION
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Patent #:
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Issue Dt:
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10/31/2017
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Application #:
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15428712
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Filing Dt:
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02/09/2017
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Title:
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CONTROLLING CHANNEL LENGTH FOR VERTICAL FETS
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Patent #:
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Issue Dt:
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10/22/2019
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Application #:
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15433309
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Filing Dt:
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02/15/2017
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Publication #:
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Pub Dt:
|
04/05/2018
| | | | |
Title:
|
REDUCED CAPACITANCE IN VERTICAL TRANSISTORS BY PREVENTING EXCESSIVE OVERLAP BETWEEN THE GATE AND THE SOURCE/DRAIN
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Patent #:
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Issue Dt:
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05/07/2019
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Application #:
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15476207
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Filing Dt:
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03/31/2017
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Publication #:
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Pub Dt:
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03/22/2018
| | | | |
Title:
|
VERTICAL FET WITH STRAINED CHANNEL
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|
Patent #:
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|
Issue Dt:
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06/09/2020
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Application #:
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15486599
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Filing Dt:
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04/13/2017
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Publication #:
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|
Pub Dt:
|
03/01/2018
| | | | |
Title:
|
VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE
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|
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Patent #:
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|
Issue Dt:
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10/01/2019
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Application #:
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15611388
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Filing Dt:
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06/01/2017
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Publication #:
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Pub Dt:
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12/28/2017
| | | | |
Title:
|
FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
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|
|
Patent #:
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|
Issue Dt:
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08/27/2019
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Application #:
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15611981
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Filing Dt:
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06/02/2017
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Publication #:
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Pub Dt:
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12/06/2018
| | | | |
Title:
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A Method of Forming Improved Vertical FET Process with Controlled Gate Length and Self-aligned Junctions
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Patent #:
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Issue Dt:
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01/01/2019
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Application #:
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15683351
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Filing Dt:
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08/22/2017
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Publication #:
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Pub Dt:
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01/25/2018
| | | | |
Title:
|
VERTICAL SCHOTTKY CONTACT FET
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|
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Patent #:
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|
Issue Dt:
|
03/19/2019
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Application #:
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15695688
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Filing Dt:
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09/05/2017
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Publication #:
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Pub Dt:
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01/11/2018
| | | | |
Title:
|
FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
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Patent #:
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|
Issue Dt:
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04/14/2020
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Application #:
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15783029
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Filing Dt:
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10/13/2017
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Publication #:
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Pub Dt:
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04/18/2019
| | | | |
Title:
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Vertical Tunnel FET with Self-Aligned Heterojunction
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Patent #:
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Issue Dt:
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06/25/2019
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Application #:
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15807751
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Filing Dt:
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11/09/2017
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Publication #:
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Pub Dt:
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04/05/2018
| | | | |
Title:
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VERTICAL FIN RESISTOR DEVICES
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|
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Patent #:
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|
Issue Dt:
|
03/12/2019
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Application #:
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15822557
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Filing Dt:
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11/27/2017
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Title:
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ONE-TIME PROGRAMMABLE VERTICAL FIELD-EFFECT TRANSISTOR
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|
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Patent #:
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|
Issue Dt:
|
06/11/2019
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Application #:
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15890699
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Filing Dt:
|
02/07/2018
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Title:
|
VERTICAL FET WITH STRAINED CHANNEL
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|
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Patent #:
|
|
Issue Dt:
|
01/21/2020
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Application #:
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16123665
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Filing Dt:
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09/06/2018
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Publication #:
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Pub Dt:
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01/17/2019
| | | | |
Title:
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FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AN ASYMMETRIC GATE STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
06/09/2020
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Application #:
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16225368
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Filing Dt:
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12/19/2018
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Publication #:
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Pub Dt:
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04/25/2019
| | | | |
Title:
|
VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE
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|
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Patent #:
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|
Issue Dt:
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10/19/2021
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Application #:
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16231717
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Filing Dt:
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12/24/2018
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Publication #:
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Pub Dt:
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05/16/2019
| | | | |
Title:
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VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT
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|
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Patent #:
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Issue Dt:
|
06/09/2020
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Application #:
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16411924
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Filing Dt:
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05/14/2019
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Publication #:
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Pub Dt:
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08/29/2019
| | | | |
Title:
|
VERTICAL FET PROCESS WITH CONTROLLED GATE LENGTH AND SELF-ALIGNED JUNCTIONS
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|
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Patent #:
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|
Issue Dt:
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10/05/2021
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Application #:
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16844131
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Filing Dt:
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04/09/2020
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Publication #:
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Pub Dt:
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07/23/2020
| | | | |
Title:
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VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE
|
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