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Total properties:
31
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09712418
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Filing Dt:
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11/13/2000
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Title:
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METHOD AND SYSTEM FOR AUTOMATICALLY GENERATING LOW LEVEL PROGRAM COMMANDS AS DEPENDENCY GRAPHS FROM HIGH LEVEL PHYSICAL DESIGN STAGES
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09714296
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Filing Dt:
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11/15/2000
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Title:
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METHOD AND SYSTEM FOR IMPLEMENTING A USER INTERFACE FOR PERFORMING PHYSICAL DESIGN OPERATIONS ON AN INTEGRATED CIRCUIT NETLIST
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09904463
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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APPARATUS FOR OPTIMIZED CONSTRAINT CHARACTERIZATION WITH DEGRADATION OPTIONS AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09909050
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Filing Dt:
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07/18/2001
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Title:
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METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEFINING AND LINKING MULTIPLE ATTACH POINTS FOR MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09909354
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Filing Dt:
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07/18/2001
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Title:
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METHOD AND SYSTEM FOR MAINTAINING ELEMENT ABSTRACTS OF AN INTEGRATED CIRCUIT NETLIST USING A MASTER LIBRARY FILE AND MODIFIABLE MASTER LIBRARY FILE
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10040852
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Filing Dt:
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12/28/2001
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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CREATING OPTIMIZED PHYSICAL IMPLEMENTATIONS FROM HIGH-LEVEL DESCRIPTIONS OF ELECTRONIC DESIGN USING PLACEMENT-BASED INFORMATION
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10097978
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Filing Dt:
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03/12/2002
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Title:
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SYSTEM AND METHOD FOR LIMITING INCREASE IN CAPACITANCE DUE TO DUMMY METAL FILLS UTILIZED FOR IMPROVING PLANAR PROFILE UNIFORMITY
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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10166944
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Filing Dt:
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06/10/2002
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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METHOD FOR GENERATING DESIGN CONSTRAINTS FOR MODULES IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN SYSTEM
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10264679
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Filing Dt:
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10/03/2002
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Title:
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METHOD OF CUSTOMIZING AND USING MAPS IN GENERATING THE PADRING LAYOUT DESIGN
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10264680
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Filing Dt:
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10/03/2002
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Title:
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METHOD OF GENERATING THE PADRING LAYOUT DESIGN USING AUTOMATION
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10264691
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Filing Dt:
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10/03/2002
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Title:
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METHOD OF OPTIMIZING PLACEMENT AND ROUTING OF EDGE LOGIC IN PADRING LAYOUT DESIGN
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10680592
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Filing Dt:
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10/07/2003
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Publication #:
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Pub Dt:
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04/07/2005
| | | | |
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Title:
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DESIGN-MANUFACTURING INTERFACE VIA A UNIFIED MODEL
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10776402
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Filing Dt:
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02/10/2004
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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REDUCTION OF CROSS-TALK NOISE IN VLSI CIRCUITS
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10812579
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Filing Dt:
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03/29/2004
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Title:
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REDUCED ARCHITECTURE PROCESSING PATHS
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Patent #:
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|
Issue Dt:
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05/01/2007
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Application #:
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10827791
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Filing Dt:
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04/19/2004
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Title:
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MODELING INTERCONNECTED PROPAGATION DELAY FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10831700
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Filing Dt:
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04/23/2004
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Title:
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FLOORPLANNING A HIERARCHICAL PHYSICAL DESIGN TO IMPROVE PLACEMENT AND ROUTING
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10855539
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Filing Dt:
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05/26/2004
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Title:
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CREATING A POWER DISTRIBUTION ARRANGEMENT WITH TAPERED METAL WIRES FOR A PHYSICAL DESIGN
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10855667
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Filing Dt:
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05/26/2004
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Title:
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OPTIMIZING LOCATIONS OF PINS FOR BLOCKS IN A HIERARCHICAL PHYSICAL DESIGN BY USING PHYSICAL DESIGN INFORMATION OF A PRIOR HIERARCHICAL PHYSICAL DESIGN
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Patent #:
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|
Issue Dt:
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04/01/2008
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Application #:
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10856268
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Filing Dt:
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05/27/2004
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Title:
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FLOW DEFINITION LANGUAGE FOR DESIGNING INTEGRATED CIRCUIT IMPLEMENTATION FLOWS
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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10861247
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Filing Dt:
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06/04/2004
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Title:
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ASYNCHRONOUS CONTROL OF MEMORY SELF TEST
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10861812
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Filing Dt:
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06/04/2004
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Title:
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REDUNDANTLY TIED METAL FILL FOR IR-DROP AND LAYOUT DENSITY OPTIMIZATION
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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10880649
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF USING STRONGLY COUPLED COMPONENTS TO ESTIMATE INTEGRATED CIRCUIT PERFORMANCE
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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10881195
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF ESTIMATING PERFORMANCE OF INTEGRATED CIRCUIT DESIGNS BY FINDING SCALARS FOR STRONGLY COUPLED COMPONENTS
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10881832
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF VECTOR GENERATION FOR ESTIMATING PERFORMANCE OF INTEGRATED CIRCUIT DESIGNS
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|
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11048287
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Filing Dt:
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01/31/2005
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Title:
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PARAMETRIC TIMING ANALYSIS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/05/2008
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Application #:
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11140914
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Filing Dt:
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06/01/2005
|
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Publication #:
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Pub Dt:
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12/01/2005
| | | | |
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Title:
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METHODS AND SYSTEMS FOR MIXED-MODE PHYSICAL SYNTHESIS IN ELECTRONIC DESIGN AUTOMATION
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|
|
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Patent #:
|
|
Issue Dt:
|
10/07/2008
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Application #:
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11372557
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Filing Dt:
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03/09/2006
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Title:
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LITHOGRAPHICALLY OPTIMIZED PLACEMENT TOOL
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|
|
|
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Patent #:
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|
Issue Dt:
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11/25/2008
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Application #:
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11451905
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Filing Dt:
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06/12/2006
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Title:
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AGGREGATE SENSITIVITY FOR STATISTICAL STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11452542
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Filing Dt:
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06/13/2006
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Publication #:
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Pub Dt:
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01/04/2007
| | | | |
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Title:
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SIGNAL FLOW DRIVEN CIRCUIT ANALYSIS AND PARTITIONING TECHNIQUE
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12129916
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Filing Dt:
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05/30/2008
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Title:
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METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING
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|
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Patent #:
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|
Issue Dt:
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08/23/2011
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Application #:
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12134849
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Filing Dt:
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06/06/2008
|
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Title:
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DYNAMIC PUSH FOR TOPOLOGICAL ROUTING OF SEMICONDUCTOR PACKAGES
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