Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014560/0445 | |
| Pages: | 3 |
| | Recorded: | 09/29/2003 | | |
| Conveyance: | WRIT OF ATTACHMENT |
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Total properties:
7
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09576105
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Filing Dt:
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05/22/2000
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Title:
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Pseudo dual-port dram for simultaneous read/write access
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09590443
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Filing Dt:
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06/09/2000
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Title:
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Read zero DRAM
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09591033
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Filing Dt:
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06/09/2000
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Title:
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Dram based refresh-free ternary cam
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09637124
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Filing Dt:
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08/11/2000
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Title:
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Structure and method of an encoded ternary content addressable memory (CAM) cell for low-power compare operation
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09660534
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Filing Dt:
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09/13/2000
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Title:
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Structure and method of a column redundancy memory
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09661165
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Filing Dt:
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09/13/2000
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Title:
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Parallel test circuit and method for wide input/output DRAM
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Patent #:
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Issue Dt:
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01/29/2002
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Application #:
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09782576
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Filing Dt:
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02/13/2001
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Title:
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Charge shared match line differential generation for CAM
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Assignee
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| 600 CALIFORNIA STREET, 6TH FL. |
| SAN FRANCISCO, CALIFORNIA 94018 |
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Correspondence name and address
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COOPER, WHITE & COOPER LLP.
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PETER C. CALIFANO, ESQ.
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201 CALIFORNIA ST.
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STE. 1700
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SAN FRANCISCO, CA 94111
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