Total properties:
200
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3
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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11734328
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Filing Dt:
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04/12/2007
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Publication #:
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Pub Dt:
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10/16/2008
| | | | |
Title:
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SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF
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Patent #:
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Issue Dt:
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01/06/2009
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Application #:
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11736231
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Filing Dt:
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04/17/2007
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Publication #:
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Pub Dt:
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09/13/2007
| | | | |
Title:
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MEMORY WITH SERIAL INPUT-OUTPUT TERMINALS FOR ADDRESS AND DATA AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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11736272
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Filing Dt:
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04/17/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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SPACE AND PROCESS EFFICIENT MRAM AND METHOD
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Patent #:
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Issue Dt:
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10/20/2009
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Application #:
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11736960
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Filing Dt:
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04/18/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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SPIN-TRANSFER MRAM STRUCTURE AND METHODS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11737270
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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BALUN SIGNAL TRANSFORMER
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Patent #:
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Issue Dt:
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05/19/2009
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Application #:
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11737492
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH A STRESSOR
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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11737496
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A STRESSOR
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11737499
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH HYDROGEN BARRIER AND METHOD THEREFOR
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Patent #:
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|
Issue Dt:
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05/12/2009
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Application #:
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11737506
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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08/16/2007
| | | | |
Title:
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ANTIFUSE CIRCUIT AND METHOD FOR SELECTIVELY PROGRAMMING THEREOF
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11737759
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Filing Dt:
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04/20/2007
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Publication #:
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Pub Dt:
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11/01/2007
| | | | |
Title:
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METHOD AND SYSTEM FOR INCORPORATING VIA REDUNDANCY IN TIMING ANALYSIS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11737761
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Filing Dt:
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04/20/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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LIGHT EMITTING ELEMENT DRIVER AND CONTROL METHOD THEREFOR
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|
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Patent #:
|
|
Issue Dt:
|
10/21/2008
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Application #:
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11738003
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Filing Dt:
|
04/20/2007
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Publication #:
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|
Pub Dt:
|
10/23/2008
| | | | |
Title:
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METHOD FOR PROCESS INTEGRATION OF NON-VOLATILE MEMORY CELL TRANSISTORS WITH TRANSISTORS OF ANOTHER TYPE
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|
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Patent #:
|
|
Issue Dt:
|
04/21/2009
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Application #:
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11738192
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Filing Dt:
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04/20/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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METHOD FOR SELECTIVE REMOVAL OF A LAYER
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|
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Patent #:
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|
Issue Dt:
|
07/28/2009
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Application #:
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11738514
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Filing Dt:
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04/22/2007
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Publication #:
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|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
METHOD OF MAKING SOLDER PAD
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|
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Patent #:
|
|
Issue Dt:
|
05/25/2010
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Application #:
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11738531
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Filing Dt:
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04/23/2007
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Publication #:
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Pub Dt:
|
11/08/2007
| | | | |
Title:
|
METHOD OF TRANSITIONING BETWEEN ACTIVE MODE AND POWER-DOWN MODE IN PROCESSOR BASED SYSTEM
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|
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Patent #:
|
|
Issue Dt:
|
10/18/2011
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Application #:
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11738683
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Filing Dt:
|
04/23/2007
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Publication #:
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|
Pub Dt:
|
10/23/2008
| | | | |
Title:
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SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE
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|
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Patent #:
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|
Issue Dt:
|
11/09/2010
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Application #:
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11739625
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Filing Dt:
|
04/24/2007
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Publication #:
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Pub Dt:
|
10/30/2008
| | | | |
Title:
|
MAGNETORESISTIVE DEVICE AND METHOD OF PACKAGING SAME
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|
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Patent #:
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|
Issue Dt:
|
09/08/2009
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Application #:
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11739933
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Filing Dt:
|
04/25/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
CURRENT SENSOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
03/23/2010
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Application #:
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11740066
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Filing Dt:
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04/25/2007
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Publication #:
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Pub Dt:
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12/13/2007
| | | | |
Title:
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ENHANCED PERMEABILITY DEVICE STRUCTURES AND METHOD
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|
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Patent #:
|
|
Issue Dt:
|
04/06/2010
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Application #:
|
11740331
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Filing Dt:
|
04/26/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH
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|
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Patent #:
|
|
Issue Dt:
|
06/15/2010
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Application #:
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11740697
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Filing Dt:
|
04/26/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
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INTEGRATED CIRCUIT WITH A PROGRAMMABLE DELAY AND A METHOD THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
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Application #:
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11741192
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Filing Dt:
|
04/27/2007
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Publication #:
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Pub Dt:
|
10/30/2008
| | | | |
Title:
|
LEVEL DETECT CIRCUIT
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|
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Patent #:
|
|
Issue Dt:
|
10/12/2010
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Application #:
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11741251
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Filing Dt:
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04/27/2007
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Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
CLOCK CONTROL MODULE SIMULATOR AND METHOD THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11741870
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Filing Dt:
|
04/30/2007
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Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SHIELDING STRUCTURES FOR SIGNAL PATHS IN ELECTRONIC DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
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Application #:
|
11741920
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Filing Dt:
|
04/30/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD
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|
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Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
11742081
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Filing Dt:
|
04/30/2007
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Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
INVERSE SLOPE ISOLATION AND DUAL SURFACE ORIENTATION INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
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Application #:
|
11742204
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Filing Dt:
|
04/30/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR RESOURCE BLOCK-SPECIFIC CONTROL SIGNALING
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|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
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Application #:
|
11742255
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Filing Dt:
|
04/30/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
TECHNIQUES FOR IMPROVING CONTROL CHANNEL ACQUISITION IN A WIRELESS COMMUNICATION SYSTEM
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11742280
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Filing Dt:
|
04/30/2007
|
Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
UE-autonomous CFI reporting
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11742291
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Filing Dt:
|
04/30/2007
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Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
CHANNEL SOUNDING TECHNIQUES FOR A WIRELESS COMMUNICATION SYSTEM
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|
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Patent #:
|
|
Issue Dt:
|
12/14/2010
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Application #:
|
11742363
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Filing Dt:
|
04/30/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS
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|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11742755
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Filing Dt:
|
05/01/2007
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Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
STEP HEIGHT REDUCTION BETWEEN SOI AND EPI FOR DSO AND BOS INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11742778
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Filing Dt:
|
05/01/2007
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
DUAL SUBSTRATE ORIENTATION OR BULK ON SOI INTEGRATIONS USING OXIDATION FOR SILICON EPITAXY SPACER FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
11742942
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Filing Dt:
|
05/01/2007
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD OF BLOCKING A VOID DURING CONTACT FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11742955
|
Filing Dt:
|
05/01/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11743157
|
Filing Dt:
|
05/02/2007
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
MULTI-RATE VITERBI DECODER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11744581
|
Filing Dt:
|
05/04/2007
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH MULTIPLE TENSILE STRESSOR LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
11744638
|
Filing Dt:
|
05/04/2007
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD OF FORMING A TRANSISTOR HAVING MULTIPLE TYPES OF SCHOTTKY JUNCTIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11745486
|
Filing Dt:
|
05/08/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING RE-CONFIGURABLE BALUN CIRCUIT AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2012
|
Application #:
|
11745875
|
Filing Dt:
|
05/08/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
CIRCUIT AND METHOD FOR GENERATING FIXED POINT VECTOR DOT PRODUCT AND MATRIX VECTOR VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11746071
|
Filing Dt:
|
05/09/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
METHOD AND CIRCUIT FOR GENERATING OUTPUT VOLTAGES FROM INPUT VOLTAGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11746118
|
Filing Dt:
|
05/09/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
ELECTRONIC DEVICE AND METHOD FOR OPERATING A MEMORY CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11746126
|
Filing Dt:
|
05/09/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
LOW VOLTAGE DATA PATH IN MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11746792
|
Filing Dt:
|
05/10/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
RADIO RECEIVER HAVING IGNITION NOISE DETECTOR AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
11746998
|
Filing Dt:
|
05/10/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
11747087
|
Filing Dt:
|
05/10/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR CONTROLLING TRANSMISSION AND EXECUTION OF COMMANDS IN AN INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11747360
|
Filing Dt:
|
05/11/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
APPARATUS FOR OPTIMIZING DIODE CONDUCTION TIME DURING A DEADTIME INTERVAL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11747414
|
Filing Dt:
|
05/11/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
BOOTSTRAP CLAMPING CIRCUIT FOR DC/DC REGULATORS AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
11748350
|
Filing Dt:
|
05/14/2007
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11748353
|
Filing Dt:
|
05/14/2007
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
11749147
|
Filing Dt:
|
05/15/2007
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHOD AND CIRCUIT FOR DRIVING H-BRIDGE THAT REDUCES SWITCHING NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11750048
|
Filing Dt:
|
05/17/2007
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROVIDING STRUCTURAL SUPPORT FOR INTERCONNECT PAD WHILE ALLOWING SIGNAL CONDUCTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11750739
|
Filing Dt:
|
05/18/2007
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
DEBUGGING A PROCESSOR THROUGH A RESET EVENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11751724
|
Filing Dt:
|
05/22/2007
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11751771
|
Filing Dt:
|
05/22/2007
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
RADIO RECEIVER HAVING A CHANNEL EQUALIZER AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11752051
|
Filing Dt:
|
05/22/2007
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
BITCELL WITH VARIABLE-CONDUCTANCE TRANSFER GATE AND METHOD THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11752544
|
Filing Dt:
|
05/23/2007
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11752608
|
Filing Dt:
|
05/23/2007
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
HIGH VOLTAGE DEEP TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11752938
|
Filing Dt:
|
05/24/2007
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR SIMULTANEOUS READS OF MULTIPLE ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
11753003
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Filing Dt:
|
05/24/2007
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Title:
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TESTER AND A METHOD FOR TESTING AN INTEGRATED CIRCUIT
|
|
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Patent #:
|
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Issue Dt:
|
08/25/2009
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Application #:
|
11753749
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Filing Dt:
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05/25/2007
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Publication #:
|
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Pub Dt:
|
11/27/2008
| | | | |
Title:
|
ANTENNA STRUCTURE FOR INTEGRATED CIRCUIT DIE USING BOND WIRE
|
|
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Patent #:
|
NONE
|
Issue Dt:
|
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Application #:
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11753851
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Filing Dt:
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05/25/2007
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Publication #:
|
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Pub Dt:
|
11/27/2008
| | | | |
Title:
|
Stress-Isolated MEMS Device and Method Therefor
|
|
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Patent #:
|
|
Issue Dt:
|
05/18/2010
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Application #:
|
11754728
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Filing Dt:
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05/29/2007
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Publication #:
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Pub Dt:
|
09/20/2007
| | | | |
Title:
|
INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
|
|
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Patent #:
|
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Issue Dt:
|
03/09/2010
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Application #:
|
11755448
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Filing Dt:
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05/30/2007
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Publication #:
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Pub Dt:
|
12/04/2008
| | | | |
Title:
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INTEGRATED CIRCUIT WITH CONTINUOUS TESTING OF REPETITIVE FUNCTIONAL BLOCKS
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11755498
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Filing Dt:
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05/30/2007
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Publication #:
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Pub Dt:
|
12/04/2008
| | | | |
Title:
|
MAGNETOELECTRONIC DEVICE HAVING ENHANCED PERMEABILITY DIELECTRIC AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2011
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Application #:
|
11755960
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Filing Dt:
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05/31/2007
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Publication #:
|
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Pub Dt:
|
12/04/2008
| | | | |
Title:
|
SYSTEMS, APPARATUS, AND METHODS FOR PERFORMING DIGITAL PRE-DISTORTION WITH FEEDBACK SIGNAL ADJUSTMENT
|
|
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Patent #:
|
|
Issue Dt:
|
06/15/2010
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Application #:
|
11756095
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Filing Dt:
|
05/31/2007
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Publication #:
|
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Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
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Application #:
|
11756187
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Filing Dt:
|
05/31/2007
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Publication #:
|
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Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METHOD FOR GENERATION, PLACEMENT, AND ROUTING OF TEST STRUCTURES IN TEST CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11756192
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Filing Dt:
|
05/31/2007
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Publication #:
|
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Pub Dt:
|
12/04/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISCHARGE RAMP RATE CONTROL AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11756197
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Filing Dt:
|
05/31/2007
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Publication #:
|
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Pub Dt:
|
12/04/2008
| | | | |
Title:
|
MULTIPLE MILLISECOND ANNEALS FOR SEMICONDUCTOR DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
11756231
|
Filing Dt:
|
05/31/2007
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Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11759028
|
Filing Dt:
|
06/06/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
ONE TIME PROGRAMMABLE ELEMENT SYSTEM IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11759463
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
LOW PASS FILTER LOW DROP-OUT VOLTAGE REGULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11759518
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
SPLIT GATE MEMORY CELL USING SIDEWALL SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11759593
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
11759935
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
HEAT SPREADER FOR CENTER GATE MOLDING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
11759944
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
METHOD AND CIRCUIT FOR REDUCING REGULATOR OUTPUT NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
11760775
|
Filing Dt:
|
06/10/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
RF POWER TRANSISTOR DEVICE WITH HIGH PERFORMANCE SHUNT CAPACITOR AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
11763107
|
Filing Dt:
|
06/14/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
OPTIMIZATION OF STORAGE DEVICE ACCESSES IN RAID SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
11763914
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
TRANSMISSION OF PACKET DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11764810
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
RECORDING DEVICE CAPABLE OF DETERMINING THE MEDIA TYPE BASED ON DETECTING THE CAPACITANCE OF PAIR ELECTRODES.
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11764911
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
Conformal EMI shielding with enhanced reliability
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
11765170
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR EMI SHIELDING IN MULTI-CHIP MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
11766880
|
Filing Dt:
|
06/22/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
PULSED STATE RETENTION POWER GATING FLIP-FLOP
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
11766888
|
Filing Dt:
|
06/22/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
TECHNIQUES FOR RESOURCE BLOCK MAPPING IN A WIRELESS COMMUNICATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
11767413
|
Filing Dt:
|
06/22/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
METHOD OF MAKING CONTACT POSTS FOR A MICROELECTROMECHANICAL DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11769376
|
Filing Dt:
|
06/27/2007
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
DISCRETE MULTI-TONE (DMT) SYSTEM AND METHOD THAT COMMUNICATES A DATA PUMP DATA STREAM BETWEEN A GENERAL PURPOSE CPU AND A DSP VIA A BUFFERING SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
11770295
|
Filing Dt:
|
06/28/2007
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11771690
|
Filing Dt:
|
06/29/2007
|
Title:
|
METHOD FOR FORMING A DUAL METAL GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
11771721
|
Filing Dt:
|
06/29/2007
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
METHOD FOR FORMING A DUAL METAL GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11784561
|
Filing Dt:
|
04/05/2007
|
Title:
|
METHODOLOGY TO REDUCE SOI FLOATING-BODY EFFECT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11785610
|
Filing Dt:
|
04/19/2007
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR OPERATING A COMMUNICATIONS SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
11788184
|
Filing Dt:
|
04/18/2007
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11788216
|
Filing Dt:
|
04/18/2007
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
METHOD TO SELECTIVELY MODULATE GATE WORK FUNCTION THROUGH SELECTIVE GE CONDENSATION AND HIGH-K DIELECTRIC LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
11800204
|
Filing Dt:
|
05/04/2007
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD TO IMPROVE SOURCE/DRAIN PARASITICS IN VERTICAL DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11803097
|
Filing Dt:
|
05/11/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
METHOD TO CONTROL UNIFORMITY/COMPOSITION OF METAL ELECTRODES, SILICIDES ON TOPOGRAPHY AND DEVICES USING THIS METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
11807745
|
Filing Dt:
|
05/29/2007
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METHOD TO FORM A VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
11807777
|
Filing Dt:
|
05/29/2007
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METHOD FOR FORMING INTERCONNECTS FOR 3-D APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11811407
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR ELECTROMIGRATION TOLERANT CELL SYNTHESIS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
11811547
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
CURRENT-MODE MEMORY CELL
|
|