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Reel/Frame:027789/0450   Pages: 14
Recorded: 03/01/2012
Attorney Dkt #:C0156-0130
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 99
1
Patent #:
Issue Dt:
12/12/1995
Application #:
07829181
Filing Dt:
01/31/1992
Title:
STRUCTURE AND METHOD FOR PROVIDING A RECONFIGURABLE EMULATION CIRCUIT WITHIOUT HOLD TIME VIOLATIONS
2
Patent #:
Issue Dt:
10/04/1994
Application #:
07896068
Filing Dt:
06/08/1992
Title:
SWITCHING MIDPLANE AND INTERCONNECTION SYSTEM FOR INTERCONNECTING LARGE NUMBERS OF SIGNALS
3
Patent #:
Issue Dt:
06/13/1995
Application #:
07947308
Filing Dt:
09/18/1992
Title:
METHOD AND APPARATUS FOR DEBUGGING RECONFIGURABLE EMULATION SYSTEMS
4
Patent #:
Issue Dt:
09/19/1995
Application #:
08000844
Filing Dt:
02/26/1993
Title:
METHOD OF REMOVING GATED CLOCKS FROM THE CLOCK NETS OF A NETLIST FOR TIMING SENSITIVE IMPLEMENTATION OF THE NETLIST IN A HARDWARE EMULATION SYSTEM
5
Patent #:
Issue Dt:
10/21/1997
Application #:
08197430
Filing Dt:
02/16/1994
Title:
METHOD AND APPARATUS FOR A TRACE BUFFER IN AN EMULATION SYSTEM
6
Patent #:
Issue Dt:
09/05/1995
Application #:
08217049
Filing Dt:
03/24/1994
Title:
MULTI-PORT MEMORY EMULATION USING TAG REGISTERS
7
Patent #:
Issue Dt:
09/19/1995
Application #:
08245310
Filing Dt:
05/17/1994
Title:
HIERARCHICALLY CONNECTED RECONFIGURABLE LOGIC ASSEMBLY
8
Patent #:
Issue Dt:
08/27/1996
Application #:
08253881
Filing Dt:
06/03/1994
Title:
MULTIPROCESSOR FOR HARDWARE EMULATION
9
Patent #:
Issue Dt:
09/05/1995
Application #:
08270234
Filing Dt:
07/01/1994
Title:
PARTIAL CROSSBAR INTERCONNECT ARCHITECTURE FOR RECONFIGURABLY CONNECTING MULTIPLE REPROGRAMMABLE LOGIC DEVICES IN A LOGIC EMULATION SYSTEM
10
Patent #:
Issue Dt:
12/19/1995
Application #:
08273513
Filing Dt:
07/11/1994
Title:
METHOD FOR EMULATING A CIRCUIT DESIGN USING AN ELECTRICALLY RECONFIGURABLE HARDWARE EMULATION APPARATUS
11
Patent #:
Issue Dt:
03/18/1997
Application #:
08470751
Filing Dt:
06/06/1995
Title:
HARDWARE LOGIC EMULATION SYSTEM WITH MEMORY CAPABILITY
12
Patent #:
Issue Dt:
08/12/1997
Application #:
08471678
Filing Dt:
06/06/1995
Title:
ROUTING METHODS FOR USE IN A LOGIC EMULATION SYSTEM
13
Patent #:
Issue Dt:
08/26/1997
Application #:
08471679
Filing Dt:
06/06/1995
Title:
STRUCTURES AND METHODS FOR ADDING STIMULUS AND RESPONSE FUNCTIONS TO A CIRCUIT DESIGN UNDERGOING EMULATION
14
Patent #:
Issue Dt:
07/15/1997
Application #:
08472531
Filing Dt:
06/07/1995
Title:
METHODS FOR CONTROLLING TIMING IN A LOGIC EMULATION SYSTEM
15
Patent #:
Issue Dt:
07/01/1997
Application #:
08483337
Filing Dt:
06/07/1995
Title:
HARDWARE LOGIC EMULATION SYSTEM CAPABLE OF PROBING INTERNAL NODES IN A CIRCUIT DESIGN UNDERGOING EMULATION
16
Patent #:
Issue Dt:
07/13/1999
Application #:
08496239
Filing Dt:
06/28/1995
Title:
EMULATION SYSTEM HAVING MULTIPLE EMULATED CLOCK CYCLES PER EMULATOR CLOCK CYCLE AND IMPROVED SIGNAL ROUTING
17
Patent #:
Issue Dt:
02/18/1997
Application #:
08497579
Filing Dt:
06/30/1995
Title:
MULTIPLE PARALLEL IMPINGEMENT FLOW COOLING WITH TUNING
18
Patent #:
Issue Dt:
10/08/1996
Application #:
08522865
Filing Dt:
09/01/1995
Title:
MULTI-PORT MEMORY EMULATION USING TAG REGISTERS
19
Patent #:
Issue Dt:
10/13/1998
Application #:
08524698
Filing Dt:
09/06/1995
Title:
A LOOK-UP TABLE BASED LOGIC ELEMENT WITH COMPLETE PERMUTABILITY OF THE INPUTS TO THE SECONDARY SIGNALS
20
Patent #:
Issue Dt:
10/06/1998
Application #:
08597197
Filing Dt:
02/06/1996
Title:
SYSTEM AND METHOD FOR EMULATING MEMORY
21
Patent #:
Issue Dt:
02/03/1998
Application #:
08638309
Filing Dt:
04/26/1996
Title:
METHOD FOR AUTOMATIC CLOCK QUALIFIER SELECTION IN REPROGRAMMABLE HARDWARE EMULATION SYSTEMS
22
Patent #:
Issue Dt:
04/22/1997
Application #:
08657921
Filing Dt:
05/31/1996
Title:
HIGH-DENSITY BOARD CONNECTOR ATTACHMENT
23
Patent #:
Issue Dt:
06/02/1998
Application #:
08662383
Filing Dt:
06/13/1996
Title:
LOGIC TRANSLATION METHOD FOR INCREASING SIMULATION/EMULATION EFFICIENCY
24
Patent #:
Issue Dt:
10/13/1998
Application #:
08672762
Filing Dt:
06/28/1996
Title:
CHECKPOINTING IN AN EMULATION SYSTEM
25
Patent #:
Issue Dt:
03/23/1999
Application #:
08718655
Filing Dt:
09/23/1996
Title:
LATCH OPTIMIZATION IN HARDWARE LOGIC EMULATION SYSTEMS
26
Patent #:
Issue Dt:
11/24/1998
Application #:
08733352
Filing Dt:
10/17/1996
Title:
METHOD AND APPARATUS FOR DESIGN VERIFICATION USING EMULATION AND SIMULATION
27
Patent #:
Issue Dt:
08/31/1999
Application #:
08742235
Filing Dt:
10/31/1996
Title:
APPARATUS AND METHOD FOR PERFORMING BEHAVIORAL MODELING IN HARDWARE EMULATION AND SIMULATION ENVIRONMENTS
28
Patent #:
Issue Dt:
07/06/1999
Application #:
08748154
Filing Dt:
11/12/1996
Title:
EMULATION SYSTEM HAVING MULTIPLE EMULATOR CLOCK CYCLES PER EMULATED CLOCK CYCLE
29
Patent #:
Issue Dt:
02/09/1999
Application #:
08761285
Filing Dt:
12/06/1996
Title:
METHODS OF USING SIMULTANEOUS TEST VERIFICATION SOFTWARE
30
Patent #:
Issue Dt:
10/05/1999
Application #:
08805852
Filing Dt:
03/03/1997
Title:
SOFTWARE RECONFIGURABLE TARGET I/O IN A CIRCUIT EMULATION SYSTEM
31
Patent #:
Issue Dt:
05/27/2003
Application #:
08824535
Filing Dt:
03/26/1997
Title:
HIGH-PERFORMANCE PROGRAMMABLE LOGIC ARCHITECTURE
32
Patent #:
Issue Dt:
03/23/1999
Application #:
08825967
Filing Dt:
04/04/1997
Title:
SWITCHING MIDPLANE AND INTERCONNECTING SYSTEM FOR INTERCONNECTING LARGE NUMBERS OF SIGNALS
33
Patent #:
Issue Dt:
10/31/2000
Application #:
08831501
Filing Dt:
03/31/1997
Title:
LOGIC ANALYSIS SUBSYSTEM IN A TIME-SLICED EMULATOR
34
Patent #:
Issue Dt:
02/09/1999
Application #:
08840357
Filing Dt:
04/28/1997
Title:
DIAGNOSTIC INTERFACE SYSTEM FOR PROGRAMMABLE LOGIC SYSTEM DEVELOPMENT
35
Patent #:
Issue Dt:
03/16/1999
Application #:
08855908
Filing Dt:
05/14/1997
Title:
METHOD AND APPARATUS FOR A TRACE BUFFER IN AN EMULATION SYSTEM
36
Patent #:
Issue Dt:
08/24/1999
Application #:
08865657
Filing Dt:
05/30/1997
Title:
DISTRIBUTED LOGIC ANALYZER FOR USE IN A HARDWARE LOGIC EMULATION SYSTEM
37
Patent #:
Issue Dt:
09/28/1999
Application #:
08865741
Filing Dt:
05/30/1997
Title:
EMULATION SYSTEM WITH TIME-MULTIPLEXED INTERCONNECT
38
Patent #:
Issue Dt:
10/19/1999
Application #:
08883025
Filing Dt:
06/25/1997
Title:
METHOD AND APPARATUS FOR CONFIGURABLE MEMORY EMULATION
39
Patent #:
Issue Dt:
03/07/2000
Application #:
08893249
Filing Dt:
07/16/1997
Title:
INPUT/OUTPUT BUFFER WITH OVERCURRENT PROTECTION CIRCUIT
40
Patent #:
Issue Dt:
11/10/1998
Application #:
08893412
Filing Dt:
07/11/1997
Title:
STRUCTURE AND METHOD FOR PROVIDING RECONFIGURABLE EMULATION CIRCUIT
41
Patent #:
Issue Dt:
02/01/2000
Application #:
08895470
Filing Dt:
07/16/1997
Title:
I/O BUFFER CIRCUIT WITH PIN MULTIPLEXING
42
Patent #:
Issue Dt:
01/04/2000
Application #:
08895516
Filing Dt:
07/16/1997
Title:
PROGRAMMABLE LOGIC DEVICE WITH MULTI-PORT MEMORY
43
Patent #:
Issue Dt:
08/17/1999
Application #:
08953315
Filing Dt:
10/17/1997
Title:
METHOD AND APPARATUS FOR EMULATING MULTI-PORTED MEMORY CIRCUITS
44
Patent #:
Issue Dt:
09/11/2001
Application #:
08968401
Filing Dt:
11/12/1997
Title:
OPTIMIZED EMULATION AND PROTOTYPING ARCHITECTURE
45
Patent #:
Issue Dt:
04/18/2000
Application #:
09052417
Filing Dt:
03/31/1998
Title:
EMULATION MODULE HAVING PLANAR ARRAY ORGANIZATION
46
Patent #:
Issue Dt:
03/07/2000
Application #:
09052732
Filing Dt:
03/31/1998
Title:
TIGHTLY COUPLED EMULATION PROCESSORS
47
Patent #:
Issue Dt:
12/14/1999
Application #:
09113628
Filing Dt:
07/10/1998
Title:
METHOD FOR PERFORMING SIMULATION USING A HARDWARE EMULATION SYSTEM
48
Patent #:
Issue Dt:
04/27/2004
Application #:
09176041
Filing Dt:
10/20/1998
Title:
MULTIPLE INSTANTIATION SYSTEM
49
Patent #:
Issue Dt:
05/02/2000
Application #:
09191228
Filing Dt:
11/12/1998
Title:
METHOD AND APPARATUS FOR DESIGN VERIFICATION USING EMULATION AND SIMULATION
50
Patent #:
Issue Dt:
02/18/2003
Application #:
09193733
Filing Dt:
11/17/1998
Title:
METHOD FOR PARTITIONING A NETLIST INTO MULTIPLE CLOCK DOMAINS
51
Patent #:
Issue Dt:
01/04/2000
Application #:
09298890
Filing Dt:
04/23/1999
Title:
PROGRAMMABLE LOGIC DEVICE WITH MULTI-PORT MEMORY
52
Patent #:
Issue Dt:
09/09/2003
Application #:
09373125
Filing Dt:
08/12/1999
Title:
CLUSTERED PROCESSORS IN AN EMULATION ENGINE
53
Patent #:
Issue Dt:
04/23/2002
Application #:
09374444
Filing Dt:
08/13/1999
Title:
EMULATION SYSTEM WITH TIME-MULTIPLEXED INTERCONNECT
54
Patent #:
Issue Dt:
04/17/2001
Application #:
09405376
Filing Dt:
09/24/1999
Title:
PROGRAMMABLE LOGIC DEVICE WITH MULTI-PORT MEMORY
55
Patent #:
Issue Dt:
11/21/2000
Application #:
09428019
Filing Dt:
10/27/1999
Title:
PROGRAMMABLE LOGIC DEVICE WITH MULTI-PORT MEMORY
56
Patent #:
Issue Dt:
09/04/2001
Application #:
09460535
Filing Dt:
12/13/1999
Title:
I/O buffer circuit with pin multiplexing
57
Patent #:
Issue Dt:
07/10/2001
Application #:
09474795
Filing Dt:
12/29/1999
Title:
INPUT/OUTPUT BUFFER WITH OVERCURRENT PROTECTION CIRCUIT
58
Patent #:
Issue Dt:
12/14/2004
Application #:
09522354
Filing Dt:
03/09/2000
Title:
NON-SYNCHRONOUS HARDWARE EMULATOR
59
Patent #:
Issue Dt:
08/24/2004
Application #:
09523053
Filing Dt:
03/10/2000
Title:
METHODS TO IMPROVE CONCURRENT BEHAVIOR MODELING WITH EMULATION
60
Patent #:
Issue Dt:
02/24/2004
Application #:
09569695
Filing Dt:
05/11/2000
Title:
EMULATION CIRCUIT WITH A HOLD TIME ALGORITHM, LOGIC ANALYZER AND SHADOW MEMORY
61
Patent #:
Issue Dt:
09/03/2002
Application #:
09570142
Filing Dt:
05/12/2000
Title:
EMULATION CIRCUIT WITH A HOLD TIME ALGORITHM, LOGIC AND ANALYZER AND SHADOW MEMORY
62
Patent #:
Issue Dt:
09/12/2006
Application #:
09655595
Filing Dt:
09/06/2000
Title:
HIGH SPEED SOFTWARE DRIVEN EMULATOR COMPRISED OF A PLURALITY OF EMULATION PROCESSORS WITH IMPROVED BOARD-TO-BOARD INTERCONNECTION CABLE LENGTH IDENTIFICATION SYSTEM
63
Patent #:
Issue Dt:
08/08/2006
Application #:
09655596
Filing Dt:
09/06/2000
Title:
HIGH SPEED SOFTWARE DRIVEN EMULATOR COMPRISED OF A PLURALITY OF EMULATION PROCESSORS WITH A METHOD TO ALLOW MEMORY READ/WRITES WITHOUT INTERRUPTING THE EMULATION
64
Patent #:
Issue Dt:
05/09/2006
Application #:
09656146
Filing Dt:
09/06/2000
Title:
HIGH SPEED SOFTWARE DRIVEN EMULATOR COMPRISED OF A PLURALITY OF EMULATION PROCESSORS WITH IMPROVED MULTIPLEXED DATA MEMORY
65
Patent #:
Issue Dt:
02/01/2005
Application #:
09656147
Filing Dt:
09/06/2000
Title:
HIGH SPEED SOFTWARE DRIVEN EMULATOR COMPRISED OF A PLURALITY OF EMULATION PROCESSORS WITH AN IMPROVED MAINTENANCE BUS THAT STREAMS DATA AT HIGH SPEED
66
Patent #:
Issue Dt:
05/31/2005
Application #:
09656541
Filing Dt:
09/06/2000
Title:
HIGH SPEED SOFTWARE DRIVEN EMULATOR COMPRISED OF A PLURALITY OF EMULATION PROCESSORS WITH A METHOD TO ALLOW HIGH SPEED BULK READ/WRITE OPERATION SYNCHRONOUS DRAM WHILE REFRESHING THE MEMORY
67
Patent #:
Issue Dt:
02/17/2004
Application #:
09695103
Filing Dt:
10/23/2000
Title:
METHOD AND APPARATUS FOR DYNAMICALLY TESTING ELECTRICAL INTERCONNECT
68
Patent #:
Issue Dt:
11/13/2001
Application #:
09748088
Filing Dt:
12/21/2000
Title:
FPGA with on-chip multiport memory
69
Patent #:
Issue Dt:
10/22/2002
Application #:
09796055
Filing Dt:
02/28/2001
Publication #:
Pub Dt:
08/29/2002
Title:
HIGH BANDWIDTH 3D MEMORY PACKAGING TECHNIQUE
70
Patent #:
Issue Dt:
03/05/2002
Application #:
09817951
Filing Dt:
03/26/2001
Publication #:
Pub Dt:
08/30/2001
Title:
PLD with on-chip memory having a shadow register
71
Patent #:
Issue Dt:
05/30/2006
Application #:
09879658
Filing Dt:
06/11/2001
Publication #:
Pub Dt:
04/25/2002
Title:
HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZED FOR EFFICIENT DATA LOADING AND UNLOADING
72
Patent #:
Issue Dt:
05/04/2004
Application #:
09922113
Filing Dt:
08/02/2001
Publication #:
Pub Dt:
10/31/2002
Title:
MEMORY CIRCUIT FOR USE IN HARDWARE EMULATION SYSTEM
73
Patent #:
Issue Dt:
09/23/2003
Application #:
09949006
Filing Dt:
09/06/2001
Publication #:
Pub Dt:
07/18/2002
Title:
OPTIMIZED EMULATION AND PROTOTYPING ARCHITECTURE
74
Patent #:
Issue Dt:
03/25/2003
Application #:
09989774
Filing Dt:
11/19/2001
Publication #:
Pub Dt:
10/31/2002
Title:
PROGRAMMABLE LOGIC DEVICE HAVING INTEGRATED PROBING STRUCTURES
75
Patent #:
Issue Dt:
01/11/2005
Application #:
10107741
Filing Dt:
03/26/2002
Publication #:
Pub Dt:
08/08/2002
Title:
APPARATUS FOR EMULATION OF ELECTPONIC SYSTEM
76
Patent #:
Issue Dt:
06/15/2010
Application #:
10128178
Filing Dt:
04/22/2002
Publication #:
Pub Dt:
04/17/2003
Title:
EMULATION SYSTEM WITH TIME-MULTIPLEXED INTERCONNECT
77
Patent #:
Issue Dt:
01/20/2004
Application #:
10246788
Filing Dt:
09/17/2002
Publication #:
Pub Dt:
05/01/2003
Title:
TIMING RESYNTHESIS IN A MULTI-CLOCK EMULATION SYSTEM
78
Patent #:
Issue Dt:
08/14/2007
Application #:
10247186
Filing Dt:
09/18/2002
Publication #:
Pub Dt:
09/11/2003
Title:
SIMULATION AND TIMING CONTROL FOR HARDWARE ACCELERATED SIMULATION
79
Patent #:
Issue Dt:
10/21/2008
Application #:
10373558
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
07/29/2004
Title:
MEMORY REWIND AND RECONSTRUCTION FOR HARDWARE EMULATOR
80
Patent #:
Issue Dt:
05/16/2006
Application #:
10459340
Filing Dt:
06/11/2003
Publication #:
Pub Dt:
11/13/2003
Title:
CLUSTERED PROCESSORS IN AN EMULATION ENGINE
81
Patent #:
Issue Dt:
08/21/2007
Application #:
10669095
Filing Dt:
09/23/2003
Publication #:
Pub Dt:
06/24/2004
Title:
LOGIC MULTIPROCESSOR FOR FPGA IMPLEMENTATION
82
Patent #:
Issue Dt:
04/08/2008
Application #:
10975676
Filing Dt:
10/28/2004
Publication #:
Pub Dt:
05/26/2005
Title:
OPTIMIZED INTERFACE FOR SIMULATION AND VISUALIZATION DATA TRANSFER BETWEEN AN EMULATION SYSTEM AND A SIMULATOR
83
Patent #:
Issue Dt:
06/15/2010
Application #:
10992165
Filing Dt:
11/17/2004
Publication #:
Pub Dt:
12/08/2005
Title:
SYSTEM AND METHOD FOR CONFIGURING COMMUNICATION SYSTEMS
84
Patent #:
Issue Dt:
06/15/2010
Application #:
10992588
Filing Dt:
11/17/2004
Publication #:
Pub Dt:
12/01/2005
Title:
SYSTEM AND METHOD FOR IDENTIFYING TARGET SYSTEMS
85
Patent #:
Issue Dt:
06/15/2010
Application #:
11047802
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
12/01/2005
Title:
METHOD OF VISUALIZATION IN PROCESSOR BASED EMULATION SYSTEM
86
Patent #:
Issue Dt:
05/23/2006
Application #:
11062047
Filing Dt:
02/18/2005
Publication #:
Pub Dt:
12/01/2005
Title:
SYSTEM AND METHOD FOR EJECTING A HIGH EXTRACTION FORCE ELECTROMECHANICAL CONNECTOR
87
Patent #:
Issue Dt:
07/22/2008
Application #:
11062170
Filing Dt:
02/18/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD AND SYSTEM FOR HARDWARE BASED REPORTING OF ASSERTION INFORMATION FOR EMULATION AND HARDWARE ACCELERATION
88
Patent #:
Issue Dt:
05/27/2008
Application #:
11133819
Filing Dt:
05/19/2005
Publication #:
Pub Dt:
12/01/2005
Title:
DYNAMIC PROGRAMMING OF TRIGGER CONDITIONS IN HARDWARE EMULATION SYSTEMS
89
Patent #:
Issue Dt:
05/18/2010
Application #:
11140714
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
12/01/2005
Title:
SYSTEM AND METHOD FOR PROVIDING FLEXIBLE SIGNAL ROUTING AND TIMING
90
Patent #:
Issue Dt:
10/21/2008
Application #:
11140722
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
12/01/2005
Title:
A SYSTEM AND METHOD FOR VALIDATING AN INPUT/OUTPUT VOLTAGE OF A TARGET SYSTEM
91
Patent #:
Issue Dt:
10/20/2009
Application #:
11141141
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
12/15/2005
Title:
SYSTEM AND METHOD FOR RESOLVING ARTIFACTS IN DIFFERENTIAL SIGNALS
92
Patent #:
Issue Dt:
12/29/2009
Application #:
11141599
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
12/01/2005
Title:
EXTENSIBLE MEMORY ARCHITECTURE AND COMMUNICATION PROTOCOL FOR SUPPORTING MULTIPLE DEVICES IN LOW-BANDWIDTH, ASYNCHRONOUS APPLICATIONS
93
Patent #:
Issue Dt:
08/18/2009
Application #:
11278794
Filing Dt:
04/05/2006
Publication #:
Pub Dt:
10/12/2006
Title:
SYSTEM AND METHOD FOR PROVIDING COMPACT MAPPING BETWEEN DISSIMILAR MEMORY SYSTEMS
94
Patent #:
Issue Dt:
06/30/2009
Application #:
11321201
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
08/24/2006
Title:
EMULATION PROCESSOR INTERCONNECTION ARCHITECTURE
95
Patent #:
Issue Dt:
06/30/2009
Application #:
11377762
Filing Dt:
03/16/2006
Publication #:
Pub Dt:
09/20/2007
Title:
METHOD AND APPARATUS FOR REWINDING EMULATED MEMORY CIRCUITS
96
Patent #:
Issue Dt:
05/28/2013
Application #:
11422314
Filing Dt:
06/05/2006
Publication #:
Pub Dt:
12/07/2006
Title:
SYSTEM AND METHOD FOR ANALYZING POWER CONSUMPTION OF ELECTRONIC DESIGN UNDERGOING EMULATION OR HARDWARE BASED SIMULATION ACCELERATION
97
Patent #:
Issue Dt:
03/27/2012
Application #:
12426164
Filing Dt:
04/17/2009
Publication #:
Pub Dt:
11/26/2009
Title:
SYSTEM AND METHOD FOR PROVIDING COMPACT MAPPING BETWEEN DISSIMILAR MEMORY SYSTEMS
98
Patent #:
Issue Dt:
05/03/2011
Application #:
12491106
Filing Dt:
06/24/2009
Publication #:
Pub Dt:
10/15/2009
Title:
SYSTEM AND METHOD FOR PROVIDING COMPACT MAPPING BETWEEN DISSIMILAR MEMORY SYSTEMS
99
Patent #:
Issue Dt:
11/26/2013
Application #:
13396849
Filing Dt:
02/15/2012
Publication #:
Pub Dt:
06/21/2012
Title:
SYSTEM AND METHOD FOR PROVIDING COMPACT MAPPING BETWEEN DISSIMILAR MEMORY SYSTEMS
Assignor
1
Exec Dt:
02/27/2012
Assignee
1
2655 SEELY AVENUE
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
JEFFREY A. MILLER
2049 CENTURY PARK EAST
SUITE 700
LOS ANGELES, CA 90067

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