Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 066087/0461 | |
| Pages: | 6 |
| | Recorded: | 01/10/2024 | | |
| Attorney Dkt #: | SDSS TO SDTECH |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14561768
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Filing Dt:
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12/05/2014
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Publication #:
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Pub Dt:
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07/02/2015
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Title:
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SPACER LAYER FOR EMBEDDING SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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15053575
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Filing Dt:
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02/25/2016
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Publication #:
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Pub Dt:
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06/23/2016
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Title:
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DISCRETE COMPONENT BACKWARD TRACEABILITY AND SEMICONDUCTOR DEVICE FORWARD TRACEABILITY
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Patent #:
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Issue Dt:
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05/07/2019
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Application #:
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15617867
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Filing Dt:
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06/08/2017
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Publication #:
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Pub Dt:
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11/22/2018
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Title:
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SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE BUMP INTERCONNECTIONS
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Patent #:
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Issue Dt:
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09/17/2019
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Application #:
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15630666
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Filing Dt:
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06/22/2017
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Publication #:
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Pub Dt:
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06/21/2018
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Title:
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SEMICONDUCTOR DEVICE INCLUDING CORNER RECESS
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Patent #:
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Issue Dt:
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11/13/2018
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Application #:
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15630712
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Filing Dt:
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06/22/2017
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Publication #:
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Pub Dt:
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06/21/2018
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Title:
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SEMICONDUCTOR DEVICE INCLUDING DIE BOND PADS AT A DIE EDGE
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Patent #:
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Issue Dt:
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11/19/2019
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Application #:
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15907600
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Filing Dt:
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02/28/2018
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Publication #:
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Pub Dt:
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07/05/2018
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Title:
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SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION
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Assignee
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| 5601 GREAT OAKS PKWY. |
| LEGAL DEP. |
| SAN JOSE, CALIFORNIA 95119 |
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Correspondence name and address
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WESTERN DIGITAL TECHNOLOGIES
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5601 GREAT OAKS PKWY
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LEGAL DEP.
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SAN JOSE, CA 95119
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