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Total properties:
20
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Patent #:
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|
Issue Dt:
|
07/02/1985
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Application #:
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06436162
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Filing Dt:
|
10/22/1982
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Title:
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SIMULATOR SYSTEM FOR LOGIC DESIGN VALIDATION
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Patent #:
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Issue Dt:
|
09/06/1988
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Application #:
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06824541
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Filing Dt:
|
01/31/1986
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Title:
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CONCURRENT FAULT SIMULATION FOR LOGIC DESIGNS
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Patent #:
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Issue Dt:
|
11/22/1988
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Application #:
|
06878459
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Filing Dt:
|
06/25/1986
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Title:
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DUAL DELAY MODE PIPELINED LOGIC SIMULATOR
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Patent #:
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Issue Dt:
|
11/22/1988
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Application #:
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06878552
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Filing Dt:
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06/26/1986
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Title:
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GLITCH DETELCTION BY FORCING THE OUTPUT OF A SIMULATED LOGIC DEVICE TO AN UNDFEFINED STATE
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Patent #:
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Issue Dt:
|
04/05/1988
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Application #:
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06916128
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Filing Dt:
|
10/07/1986
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|
Title:
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PROGRAMMABLE LOOK UP SYSTEM
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Patent #:
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Issue Dt:
|
06/30/1992
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Application #:
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07467297
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Filing Dt:
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01/18/1990
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Title:
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HIGH SPEED LOGIC SIMULATION SYSTEM WITH STIMULUS ENGINE USING INDEPENDENT EVENT CHANNELS SELECTIVLY DRIVEN BY INDEPENDENT STIMULUS PROGRAMS
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Patent #:
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Issue Dt:
|
08/19/1997
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Application #:
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08344723
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Filing Dt:
|
11/23/1994
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Title:
|
PIPE-LINED STATIC ROUTER AND SCHEDULER FOR CONFIGURABLE LOGIC SYSTEM PERFORMING SIMULTANEOUS COMMUNICATIONS AND COMPUTATION
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|
|
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Patent #:
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|
Issue Dt:
|
07/15/1997
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Application #:
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08513605
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Filing Dt:
|
08/10/1995
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Title:
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TRANSITION ANALYSIS AND CIRCUIT RESYNTHESIS METHOD AND DEVICE FOR DIGITAL CIRCUIT MODELING
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|
|
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Patent #:
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|
Issue Dt:
|
09/01/1998
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Application #:
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08574259
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Filing Dt:
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12/18/1995
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Title:
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LOGIC ANALYSIS SYSTEM FOR LOGIC EMULATION SYSTEMS
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|
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Patent #:
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|
Issue Dt:
|
12/29/1998
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Application #:
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08588649
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Filing Dt:
|
01/19/1996
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Title:
|
CIRCUIT PARTITIONING TECHNIQUE FOR USE WITH MULTIPLEXED INTER- CONNECTIONS
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|
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Patent #:
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Issue Dt:
|
12/08/1998
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Application #:
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08780527
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Filing Dt:
|
01/08/1997
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Title:
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PROGRAMMABLE MULTIPLEXING INPUT/OUTPUT PORT
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|
|
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Patent #:
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Issue Dt:
|
12/15/1998
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Application #:
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08806542
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Filing Dt:
|
02/24/1997
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|
Title:
|
PIPE LINED STATIC ROUTER AND SCHEDULER FOR CONFIGURABLE LOGIC SYSTEM PERFORMING SIMULTANEOUS COMMUNICATIONS AND COMPUTATION
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
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08807298
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Filing Dt:
|
02/27/1997
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|
Title:
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METHOD FOR AVOIDING BUS CONTENTION IN A DIGITAL CIRCUIT
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/28/1999
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Application #:
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08863963
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Filing Dt:
|
05/27/1997
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|
Title:
|
TRANSITION ANALYSIS AND CIRCUIT RESYNTHESIS METHOD AND DEVICE FOR DIGITAL CIRCUIT MODELING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
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Application #:
|
09097138
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Filing Dt:
|
06/12/1998
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|
Title:
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RECONSTRUCTION ENGINE FOR A HARDWARE CIRCUIT EMULATOR
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|
|
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Patent #:
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|
Issue Dt:
|
04/24/2001
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Application #:
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09133959
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Filing Dt:
|
08/14/1998
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|
Title:
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LOGIC ANALYSIS SYSTEM FOR LOGIC EMULATION SYSTEMS
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
09804504
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Filing Dt:
|
03/12/2001
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|
Publication #:
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Pub Dt:
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07/26/2001
| | | | |
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Title:
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Logic analysis system for logic emulation systems
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|
|
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Patent #:
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|
Issue Dt:
|
05/27/2008
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Application #:
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09841974
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Filing Dt:
|
04/24/2001
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Publication #:
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Pub Dt:
|
10/24/2002
| | | | |
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Title:
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EMULATOR WITH SWITCHING NETWORK CONNECTIONS
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/09/2004
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Application #:
|
10103617
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Filing Dt:
|
03/20/2002
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|
Title:
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FUNCTIONAL VERIFICATION OF LOGIC AND MEMORY CIRCUITS WITH MULTIPLE ASYNCHRONOUS DOMAINS
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|
|
|
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Patent #:
|
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Issue Dt:
|
11/28/2006
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Application #:
|
10701598
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Filing Dt:
|
11/06/2003
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Title:
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FUNCTIONAL VERIFICATION OF LOGIC AND MEMORY CIRCUITS WITH MULTIPLE ASYNCHRONOUS DOMAINS
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