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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08599075
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Filing Dt:
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02/09/1996
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Title:
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HIDDEN PRECHARGE PSEUDO CACHE DRAM
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08681718
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Filing Dt:
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07/29/1996
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Title:
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METHOD AND APPARATUS FOR PREVENTING PARTICLE CONTAMINATION IN A PROCESS CHAMBER
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08953609
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Filing Dt:
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10/17/1997
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Title:
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MOSFET WITH SELF-ALIGNED SILICIDATION AND GATE-SIDE AIR-GAP STRUCTURE
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08954412
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Filing Dt:
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10/20/1997
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Title:
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METHOD FOR FORMING A DRAM CELL WITH A DOUBLE-CROWN SHAPED CAPACITOR
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08954413
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Filing Dt:
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10/20/1997
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Title:
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METHOD FOR FORMING A DRAM CELL WITH A MULTIPLE PILLAR-SHAPED CAPACITOR
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08954416
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Filing Dt:
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10/20/1997
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Title:
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METHOD OF MAKING DEEP SUB-MICRON METER MOSFET WITH A HIGH PERMITIVITY GATE DIELECTRIC
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08958536
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Filing Dt:
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10/27/1997
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Title:
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METHOD FOR FORMING A DRAM CELL WITH A FORK-SHAPED CAPACITOR
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Patent #:
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Issue Dt:
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01/04/2000
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Application #:
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08960870
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Filing Dt:
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10/31/1997
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Title:
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DOUBLE STAIR-LIKE CAPACITOR STRUCTURE FOR A DRAM CELL
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08962003
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Filing Dt:
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10/31/1997
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Title:
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DRAM CELL WITH A RUGGED STACKED TRENCH (RST) CAPACITOR
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08962623
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Filing Dt:
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11/03/1997
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Title:
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METHOD FOR FORMING A DRAM CELL WITH A RAGGED POLYSILICON CROWN-SHAPED CAPACITOR
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Patent #:
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Issue Dt:
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09/15/1998
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Application #:
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08962625
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Filing Dt:
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11/03/1997
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Title:
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METHOD OF MAKING A DOUBLE STAIR-LIKE CAPACITOR FOR A HIGH DENSITY DRAM CELL
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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08984871
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Filing Dt:
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12/04/1997
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Title:
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SELF-ALIGNED SILICIDED MOSFETS WITH A GRADED S/D JUNCTION AND GATE-SIDE AIR-GAP STRUCTURE
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08988031
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Filing Dt:
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12/10/1997
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Title:
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METHOFOR A RING-LIKE CAPACITOR IN A SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08988034
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Filing Dt:
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12/10/1997
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Title:
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METHOD FOR FORMING SHALLOW TRENCH ISOLATION WITH GLOBAL PLANARIZATION
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Patent #:
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Issue Dt:
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10/06/1998
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Application #:
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08988035
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Filing Dt:
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12/10/1997
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Title:
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METHOD OF FORMING A T-GATE LIGHTLY-DOPED DRAIN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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08988518
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Filing Dt:
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12/10/1997
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Title:
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CIRCUIT OF REDUCING TRANSMISSION DELAY FOR SYNCHRONOUS DRAM
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08990117
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Filing Dt:
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12/12/1997
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Title:
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METHOD OF MANUFACTURING TRENCH DRAM CELLS WITH SELF-ALIGNED FIELD PLATE
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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08990167
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Filing Dt:
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12/12/1997
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Title:
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SELF-ALIGNED SILICIDED MOS TRANSISTOR WITH A LIGHTLY DOPED DRAIN BALLAST RESISTOR FOR ESD PROTECTION
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Patent #:
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Issue Dt:
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01/05/1999
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Application #:
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08994053
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Filing Dt:
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12/19/1997
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Title:
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METHOD OF MAKING ULTRA-SHORT CHANNEL MOSFET WITH SELF-ALIGNED SILICIDED CONTACT AND EXTENDED S/D JUNCTION
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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08994178
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Filing Dt:
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12/19/1997
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Title:
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METHOD OF FORMING A SELF-ALIGNED SILICIDE MOSFET WITH AN EXTENDED ULTRA-SHALLOW S/D JUNCTION
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08995569
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Filing Dt:
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12/22/1997
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Title:
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METHOD OF MAKING A MULTIPLE MUSHROOM SHAPE CAPACITOR FOR HIGH DENSITY DRAMS
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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08996694
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Filing Dt:
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12/23/1997
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Title:
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METHOD OF MAKING SELF-ALIGNED SILICIDED MOS TRANSISTOR WITH ESD PROTECTION IMPROVEMENT
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08998796
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Filing Dt:
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12/29/1997
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Title:
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METHOD OF MAKING MOS TRANSISTORS WITH A GATE-SIDE AIR-GAP STRUCTURE AND AN EXTENSION ULTRA-SHALLOW S/D JUNCTION
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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08998933
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Filing Dt:
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12/29/1997
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Title:
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METHOD OF FABRICATING DRAM CELL WITH CAPACITOR HAVING MULTIPLE CONCAVE STRUCTURE
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08999268
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Filing Dt:
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12/29/1997
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Title:
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METHOD TO FORM STACKED-SI GATE PMOSFETS WITH ELEVATED AND EXTENDED S/D JUNCTION
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08999449
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Filing Dt:
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12/29/1997
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Title:
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DRAM CELL WITH A MULTIPLE MUSHROOM-SHAPED CAPACITOR
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09001978
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Filing Dt:
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12/31/1997
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Title:
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METHOD OF FABRICATING CMOS TRANSISTORS WITH A PLANAR SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09002607
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Filing Dt:
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01/05/1998
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Title:
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METHOD TO FORM HIGH DENSITY NAND STRUCTURE NONVOLATILE MEMORIES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09002608
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Filing Dt:
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01/05/1998
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Title:
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METHOD OF FORMING MOSFETS WITH RECESSED SELF-ALIGNED SILICIDE GRADUAL S/D JUNCTION
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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09004448
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Filing Dt:
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01/08/1998
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Title:
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AN ULTRA-SHORT CHANNEL RECESSED GATE MOSFET WITH A BURIED CONTACT
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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09004449
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Filing Dt:
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01/08/1998
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Title:
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PROCESS TO FABRICATE ULTRA-SHORT CHANNEL NMOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09013424
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Filing Dt:
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01/16/1998
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Title:
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DISCHARGE LAMP FOR AN AUTOMOTIVE VEHICLE
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09013425
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Filing Dt:
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01/26/1998
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Title:
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METHOD TO FORM DIFFERENT THRESHOLD NMOSFETS FOR READ ONLY MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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09013429
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Filing Dt:
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01/26/1998
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Title:
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METHOD TO FORM ELEVATED SOURCE/DRAIN WITH SOLID PHASE DIFFUSED SOURCE/DRAIN EXTENSION FOR MOSFET
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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09013676
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Filing Dt:
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01/26/1998
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Title:
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REDUCED MASK CMOS SALICIDED PROCESS
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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09013682
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Filing Dt:
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01/26/1998
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Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH AN INVERSE-T GATE LIGHTLY-DOPED DRAIN STRUCTURE
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09013689
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Filing Dt:
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01/26/1998
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Title:
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METHOD OF FORMING A TRENCH CAPACITOR FOR A DRAM CELL
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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09013690
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Filing Dt:
|
01/26/1998
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Title:
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DRAM CELL WITH A FORK-SHAPED CAPACITOR
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Patent #:
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Issue Dt:
|
09/22/1998
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Application #:
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09013691
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Filing Dt:
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01/26/1998
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Title:
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METHOD FOR FORMING A SEMICODUCTOR DEVICE WITH A GRADED LIGHTLY-DOPED DRAIN STRUCTURE
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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09013694
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Filing Dt:
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01/26/1998
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Title:
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PROCESS TO FORM CMOS DEVICES WITH HIGHER ESD AND HOT CARRIER IMMUNITY
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Patent #:
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|
Issue Dt:
|
05/02/2000
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Application #:
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09014862
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Filing Dt:
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01/28/1998
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Title:
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METHOD TO FORM A RAGGED POLY-SI STRUCTURE FOR HIGH DENSITY DRAM CELLS
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Patent #:
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Issue Dt:
|
05/16/2000
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Application #:
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09014864
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Filing Dt:
|
01/28/1998
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Title:
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METHOD TO SIMULATANEOUSLY FABRICATE THE SELF-ALIGNED SILICIDED DEVICES AND ESD PROTECTIVE DEVICES
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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09014865
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Filing Dt:
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01/28/1998
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Title:
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CMOS PROCESS FOR FORMING PLANARIZED TWIN WELLS
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09014866
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Filing Dt:
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01/28/1998
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Title:
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METHOD FOR FORMING A STRESS-FREE SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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09014867
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Filing Dt:
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01/28/1998
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Title:
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ULTRA-SHORT CHANNEL RECESSED GATE MOSFET WITH A BURIED CONTACT
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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09014868
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Filing Dt:
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01/28/1998
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Title:
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STRESS-FREE SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09020229
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Filing Dt:
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02/06/1998
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Title:
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METHOD TO FABRICATE DEEP SUB-UM CMOSFETS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09020230
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Filing Dt:
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02/06/1998
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Title:
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HIGH DENSITY NAND STRUCTURE NONVOLATILE MEMORIES
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09023260
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Filing Dt:
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02/13/1998
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Title:
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DUAL DAMASCENE MULTI-LEVEL METALLIZATION AND INTERCONNECTION STRUCTURE
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09023261
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Filing Dt:
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02/13/1998
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Title:
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DUAL DAMASCENE PROCESS FOR MULTI-LEVEL METALLIZATION AND INTERCONNECTION STRUCTURE
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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09023453
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Filing Dt:
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02/13/1998
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Title:
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METHOD TO FORM A CAPACITOR FOR HIGH DENSITY DRAM CELL
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Patent #:
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Issue Dt:
|
11/30/1999
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Application #:
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09023454
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Filing Dt:
|
02/13/1998
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Title:
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MOSFETS WITH RECESSED SELF-ALIGNED SILICIDE GRADUAL S/D JUNCTION
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Patent #:
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Issue Dt:
|
07/06/1999
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Application #:
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09024772
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Filing Dt:
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02/17/1998
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Title:
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METHOD TO FABRICATE SHORT-CHANNEL MOSFETS WITH AN IMPROVEMENT IN ESD RESISTANCE
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Patent #:
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Issue Dt:
|
05/16/2000
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Application #:
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09025969
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Filing Dt:
|
02/19/1998
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Title:
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MOSFETS WITH A RECESSED SELF-ALIGNED SILICIDE CONTACT AND AN EXTENDED SOURCE/DRAIN JUNCTION
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Patent #:
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Issue Dt:
|
12/21/1999
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Application #:
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09025970
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Filing Dt:
|
02/19/1998
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Title:
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DRAM CELL WITH A DOUBLE-CROWN SHAPED CAPACITOR
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Patent #:
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Issue Dt:
|
11/30/1999
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Application #:
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09025971
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Filing Dt:
|
02/19/1998
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Title:
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METHOD FOR FORMING SELF-ALIGNED SILICIDED MOS TRANSISTORS WITH ASYMMETRIC ESD PROTECTING TRANSISTORS
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Patent #:
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Issue Dt:
|
07/04/2000
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Application #:
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09032008
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Filing Dt:
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02/27/1998
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Title:
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METHOD TO MANUFACTURE NONVOLATILE MEMORIES WITH A TRENCH-PILLAR CELL STRUCTURE FOR HIGH CAPACITIVE COUPLING RATIO
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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09033526
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Filing Dt:
|
03/02/1998
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|
Title:
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ELEVATED SOURCE/DRAIN MOSFET WITH SOLID PHASE DIFFUSED SOURCE/DRAIN EXTENSION
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|
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Patent #:
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|
Issue Dt:
|
01/04/2000
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Application #:
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09033527
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Filing Dt:
|
03/02/1998
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Title:
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METHOD OF MAKING NANOMETER SI ISLANDS FOR SINGLE ELECTRON TRANSISTORS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09033546
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Filing Dt:
|
03/02/1998
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Title:
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HIGH DENSITY AND LOW POWER FLASH MEMORIES WITH A HIGH CAPACITIVE-COUPLING RATIO
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Patent #:
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Issue Dt:
|
09/12/2000
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Application #:
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09033560
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Filing Dt:
|
03/02/1998
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Title:
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METHOD OF MAKING SINGLE-ELECTRON-TUNNELING CMOS TRANSISTORS
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Patent #:
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Issue Dt:
|
12/14/1999
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Application #:
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09033948
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Filing Dt:
|
03/02/1998
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Title:
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METHOD TO FORM ULTRA-SHORT CHANNEL MOSFET WITH A GATE-SIDE AIRGAP STRUCTURE
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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09034635
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Filing Dt:
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03/04/1998
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Title:
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METHOD FOR FORMING AN ISOLATION REGION IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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09036027
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Filing Dt:
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03/06/1998
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Title:
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METHOD OF FORMING HIGH CAPACITIVE-COUPLING RATIO AND HIGH SPEED FLASH MEMORIES WITH A TEXTURED TUNNEL OXIDE
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09042347
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Filing Dt:
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03/13/1998
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Title:
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METHOD FOR FORMING HIGH DENSITY NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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09042348
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Filing Dt:
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03/13/1998
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Title:
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METHOD TO FORM ULTRA-SHORT CHANNEL ELEVATED S/D MOSFETS ON AN ULTRA-THIN SOI SUBSTRATE
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Patent #:
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Issue Dt:
|
12/07/1999
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Application #:
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09042349
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Filing Dt:
|
03/13/1998
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Title:
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METHOD TO FORM GLOBAL PLANARIZED SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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09042351
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Filing Dt:
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03/13/1998
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Title:
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LOW MASK COUNT SELF-ALIGNED SILICIDED CMOS TRANSISTORS WITH A HIGH ELECTROSTATIC DISCHARGE RESISTANCE
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Patent #:
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Issue Dt:
|
08/01/2000
|
Application #:
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09042352
|
Filing Dt:
|
03/13/1998
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|
Title:
|
METHOD TO FABRICATE DUAL THRESHOLD CMOS CIRCUITS
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/02/1999
|
Application #:
|
09046331
|
Filing Dt:
|
03/23/1998
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|
Title:
|
3-D CMOS TRANSISTORS WITH HIGH ESD RELIABILITY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09046332
|
Filing Dt:
|
03/23/1998
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|
Title:
|
BLANKET WELL COUNTER DOPING PROCESS FOR HIGH SPEED/LOW POWER MOSFETS
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|
|
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Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09046343
|
Filing Dt:
|
03/23/1998
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|
Title:
|
HIGH DENSITY/SPEED NONVOLATILE MEMORIES WITH A TEXTURED TUNNEL OXIDE AND A HIGH CAPACITIVE-COUPLING RATIO
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
09048154
|
Filing Dt:
|
03/25/1998
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|
Title:
|
METHOD OF FORMING DEEP SUB-MICRON CMOS TRANSISTORS WITH SELF-ALIGNED SILICIDED CONTACT AND EXTENDED S/D JUNCTION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/28/1999
|
Application #:
|
09048549
|
Filing Dt:
|
03/25/1998
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|
Title:
|
METHOD FOR FORMING A HIGH DENSITY SHALLOW TRENCH CONTACTLESS NONVOLATILE MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09050540
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
HIGH DENSITY SHALLOW TRENCH CONTACTLESS NONVOLITILE MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
09050541
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
METHOD OF MAKING SELF-ALIGNED SILICIDE CMOS TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09050668
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
MOSFETS STRUCTURE WITH A RECESSED SELF-ALIGNED SILICIDE CONTACT AND AN EXTENDED SOURCE/DRAIN JUNCTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
09050669
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH AN INVERSE-T GATE LIGHTLY-DOPED DRAIN STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09050670
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
ULTRA-SHORT CHANNEL NMOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
09052280
|
Filing Dt:
|
03/31/1998
|
|
Title:
|
CMOS TRANSISTORS WITH SELF-ALIGNED PLANARIZATION TWIN-WELL BY USING FEWER MASK COUNTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
09054128
|
Filing Dt:
|
04/02/1998
|
|
Title:
|
METHOD FOR MANUFACTURING A CAPACITOR OF A TRENCH DTAM CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09056222
|
Filing Dt:
|
04/07/1998
|
|
Title:
|
METHOD TO SIMULTANEOUSLY FABRICATE THE SELF-ALIGNED SILICIDED DEVICES AND ESD PROTECTION DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09057866
|
Filing Dt:
|
04/09/1998
|
|
Title:
|
PROCESS TO FABRICATE THE NON-SILICIDE REGION FOR ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09057867
|
Filing Dt:
|
04/09/1998
|
|
Title:
|
LOW MASK COUNT PROCESS TO FABRICATE MASK READ ONLY MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09057869
|
Filing Dt:
|
04/09/1998
|
|
Title:
|
SINGLE ELECTRON TRANSISTOR MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09060565
|
Filing Dt:
|
04/14/1998
|
|
Title:
|
STACKED CAPACITOR STRUCTURE FOR HIGH DENSITY DRAM CELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
09060566
|
Filing Dt:
|
04/14/1998
|
|
Title:
|
MANUFACTURING METHOD FOR MASK ROM DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09062827
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
3-D CMOS TRANSISTORS WITH HIGH ESD RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09062829
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
SELF-ALIGNED SILICIDED MOS DEVICES WITH AN EXTENDED S/D JUNCTION AND AN ESD PROTECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09063210
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
SHALLOW TRENCH ISOLATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
09063211
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
DOUBLE CODING PROCESSES FOR MASK READ ONLY MEMORY (ROM) DEVICES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/01/2000
|
Application #:
|
09064261
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
PROCESS TO FABRICATE PLANARIZED DEEP-SHALLOW TRENCH ISOLATION HAVING U PPER AND LOWER PORTIONS WITH OXIDIZED SEMICONDUCTOR TRENCH FILL IN THE UPPER PORTION AND SEMICONDUCTOR TRENCH FILL IN THE LOWER PORTION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/09/1999
|
Application #:
|
09064262
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
METHOD TO FORM MOSFET WITH AN INVERSE T-SHAPED AIR-GAP GATE STRUCTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09064430
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
METHOD OF ELIMINATING BURIED CONTACT TRENCH IN SRAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09064976
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
PLANARIZED DEEP-SHALLOW TRENCH ISOLATION FOR CMOS/BIPOLAR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09065323
|
Filing Dt:
|
04/23/1998
|
|
Title:
|
TRENCH-FREE BURIED CONTACT FOR SRAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09065472
|
Filing Dt:
|
04/23/1998
|
|
Title:
|
ULTRA-SHORT CHANNEL ELEVATED S/D MOSFETS FORMED ON AN ULTRA-THIN SOI SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2001
|
Application #:
|
09072289
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
FIPOS METHOD OF FORMING SOI CMOS STRUCTURE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
12/26/2000
|
Application #:
|
09072290
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
METHOD TO FORM SHALLOW TRENCH ISOLATION WITH AN OXYNITRIDE BUFFER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09072291
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
DOUBLE CODING MASK READ ONLY MEMORY (MASK ROM) FOR MINIMIZING BAND-TO-BAND LEAKAGE
|
|
