Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 022345/0473 | |
| Pages: | 9 |
| | Recorded: | 03/04/2009 | | |
| Attorney Dkt #: | 3222.194STR0 (EXHIBIT 2) |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09840026
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Filing Dt:
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04/24/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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RISC microprocessor architecture implementing multiple register sets
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11252820
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Filing Dt:
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10/19/2005
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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Superscalar RISC instruction scheduling
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Assignee
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| 502 E. JOHN STREET |
| CARSON CITY, NEVADA 89706 |
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Correspondence name and address
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STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
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1100 NEW YORK AVENUE, N.W.
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WASHINGTON, DC 20005
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