|
Total properties:
56
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
08817876
|
Filing Dt:
|
07/24/1997
|
|
Title:
|
WAVELENGTH SELECTIVE FILTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
09914944
|
Filing Dt:
|
11/25/2003
|
|
Title:
|
CONFIGURABLE APERIODIC GRATING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10064002
|
Filing Dt:
|
06/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
FARBY-PEROT LASER WITH WAVELENGTH CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10647060
|
Filing Dt:
|
08/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10647061
|
Filing Dt:
|
08/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10647069
|
Filing Dt:
|
08/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING MOSFET HAVING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10683888
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/21/2004
| | | | |
|
Title:
|
OPTICAL FILTER DEVICE WITH APERIODICALLY ARRANGED GRATING ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10716783
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10716991
|
Filing Dt:
|
11/19/2003
|
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2005
|
Application #:
|
10716994
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10717370
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10717374
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10717375
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10936903
|
Filing Dt:
|
09/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING AN ACTIVE OPTICAL DEVICE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
10936913
|
Filing Dt:
|
09/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
ELECTRONIC DEVICE COMPRISING ACTIVE OPTICAL DEVICES WITH AN ENERGY BAND ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10936920
|
Filing Dt:
|
09/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
METHOD FOR MAKING AN INTEGRATED CIRCUIT COMPRISING A WAVEGUIDE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10937071
|
Filing Dt:
|
09/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING A WAVEGUIDE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10940418
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE CHANNEL VERTICALLY STEPPED ABOVE SOURCE AND DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
10940426
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE CHANNEL VERTICALLY STEPPED ABOVE SOURCE AND DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10940594
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE WITH UPPER PORTIONS EXTENDING ABOVE ADJACENT UPPER PORTIONS OF SOURCE AND DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10941062
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE WITH UPPER PORTIONS EXTENDING ABOVE ADJACENT UPPER PORTIONS OF SOURCE AND DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10992186
|
Filing Dt:
|
11/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE HAVING 3/1-5/1 GERMANIUM LAYER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10992422
|
Filing Dt:
|
11/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE HAVING 3/1-5/1 GERMANIUM LAYER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11042270
|
Filing Dt:
|
01/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A MOSFET HAVING A BAND-ENGINEERED SUPERLATTICE WITH A SEMICONDUCTOR CAP LAYER PROVIDING A CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11042272
|
Filing Dt:
|
01/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MOSFET HAVING A BAND-ENGINEERED SUPERLATTICE WITH A SEMICONDUCTOR CAP LAYER PROVIDING A CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11089950
|
Filing Dt:
|
03/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING MOSFET HAVING BAND-ENGINEERED SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
11096828
|
Filing Dt:
|
04/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ADJACENT SEMICONDUCTOR LAYER WITH DOPED REGIONS DEFINING A SEMICONDUCTOR JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
11097433
|
Filing Dt:
|
04/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE WITH REGIONS DEFINING A SEMICONDUCTOR JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11097588
|
Filing Dt:
|
04/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ADJACENT SEMICONDUCTOR LAYER WITH DOPED REGIONS DEFINING A SEMICONDUCTOR JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
11097612
|
Filing Dt:
|
04/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE WITH REGIONS DEFINING A SEMICONDUCTOR JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11136747
|
Filing Dt:
|
05/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE DIELECTRIC INTERFACE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11136834
|
Filing Dt:
|
05/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE USING INTERMEDIATE ANNEALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11381787
|
Filing Dt:
|
05/05/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11381835
|
Filing Dt:
|
05/05/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11420876
|
Filing Dt:
|
05/30/2006
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11421234
|
Filing Dt:
|
05/31/2006
|
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
|
Title:
|
MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE INCLUDING A SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11425209
|
Filing Dt:
|
06/20/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH A SUPERLATTICE THEREBETWEEN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11426969
|
Filing Dt:
|
06/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
|
Title:
|
FINFET INCLUDING A SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11428003
|
Filing Dt:
|
06/30/2006
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11457256
|
Filing Dt:
|
07/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE LAYER ABOVE A STRESS LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11457269
|
Filing Dt:
|
07/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE BETWEEN AT LEAST ONE PAIR OF SPACED APART STRESS REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11457286
|
Filing Dt:
|
07/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE AND OVERLYING STRESS LAYER AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11534298
|
Filing Dt:
|
09/22/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING REGIONS OF BAND-ENGINEERED SEMICONDUCTOR SUPERLATTICE TO REDUCE DEVICE-ON RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11534343
|
Filing Dt:
|
09/22/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING REGIONS OF BAND-ENGINEERED SEMICONDUCTOR SUPERLATTICE TO REDUCE DEVICE-ON RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11614513
|
Filing Dt:
|
12/21/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
|
Title:
|
METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11675833
|
Filing Dt:
|
02/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
|
Title:
|
MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11675846
|
Filing Dt:
|
02/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
|
Title:
|
METHOD FOR MAKING A MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11677098
|
Filing Dt:
|
02/21/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11677099
|
Filing Dt:
|
02/21/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11687430
|
Filing Dt:
|
03/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
|
Title:
|
METHODS OF MAKING SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12018255
|
Filing Dt:
|
01/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A METAL-TO-SEMICONDUCTOR SUPERLATTICE INTERFACE LAYER AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
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Application #:
|
12018260
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Filing Dt:
|
01/23/2008
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
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SEMICONDUCTOR DEVICE WITH A VERTICAL MOSFET INCLUDING A SUPERLATTICE AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12102305
|
Filing Dt:
|
04/14/2008
|
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Publication #:
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Pub Dt:
|
10/23/2008
| | | | |
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Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH MASKLESS SUPERLATTICE DEPOSITION FOLLOWING STI FORMATION AND RELATED STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13017863
|
Filing Dt:
|
01/31/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
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Title:
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MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14550244
|
Filing Dt:
|
11/21/2014
|
|
Publication #:
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|
Pub Dt:
|
05/28/2015
| | | | |
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Title:
|
VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14550272
|
Filing Dt:
|
11/21/2014
|
|
Publication #:
|
|
Pub Dt:
|
05/28/2015
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|
Title:
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SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE DEPLETION LAYER STACK AND RELATED METHODS
|
|
