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Total properties:
20
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08804524
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Filing Dt:
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02/21/1997
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Title:
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A SYSTEM AND METHOD FOR EXTRACTING PARASITIC IMPEDANCE FROM AN INTEGRATED CIRCUIT LAYOUT
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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08937393
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Filing Dt:
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09/25/1997
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Title:
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METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09245812
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Filing Dt:
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02/04/1999
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Title:
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METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09373923
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Filing Dt:
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08/12/1999
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Title:
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METHOD FOR DETERMINING ON-CHIP SHEET RESISTIVITY
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09375254
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Filing Dt:
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08/16/1999
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Title:
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METHOD AND APPARATUS FOR LOGIC SYNTHESIS (INFERRING COMPLEX COMPONENTS)
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09375836
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Filing Dt:
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08/16/1999
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Title:
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METHOD AND APPARATUS FOR LOGIC SYNTHESIS (WORD ORIENTED NETLIST)
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09516489
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Filing Dt:
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03/01/2000
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Title:
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METHOD AND APPARATUS FOR INTERCONNECT-DRIVEN OPTIMIZATION OF INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09798016
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Filing Dt:
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02/28/2001
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Title:
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RTL POWER ANALYSIS USING GATE-LEVEL CELL POWER MODELS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10008458
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Filing Dt:
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11/30/2001
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Title:
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CIRCUIT OPTIMIZATION FOR MINIMUM PATH TIMING VIOLATIONS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10022743
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Filing Dt:
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12/14/2001
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Title:
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METHOD FOR MATCH DELAY BUFFER INSERTION
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|
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10022747
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Filing Dt:
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12/14/2001
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Title:
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METHOD FOR OPTIMAL DRIVER SELECTION
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10022751
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Filing Dt:
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12/14/2001
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Title:
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METHOD FOR DETERMINING A ZERO-SKEW BUFFER INSERTION POINT
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10023329
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Filing Dt:
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12/14/2001
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Title:
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METHOD FOR BALANCED-DELAY CLOCK TREE INSERTION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10057165
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Filing Dt:
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01/24/2002
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Publication #:
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Pub Dt:
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08/01/2002
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Title:
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METHOD AND SYSTEM FOR EXTRACTION OF PARASITIC INTERCONNECT IMPEDANCE INCLUDING INDUCTANCE
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10262914
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Filing Dt:
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10/01/2002
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Title:
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VECTORLESS INSTANTANEOUS CURRENT ESTIMATION
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|
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10387644
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Filing Dt:
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03/12/2003
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Publication #:
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Pub Dt:
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09/18/2003
| | | | |
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Title:
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METHOD AND APPARATUS FOR INTERCONNECT-DRIVEN OPTIMIZATION OF INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10447076
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Filing Dt:
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05/27/2003
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Publication #:
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Pub Dt:
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11/06/2003
| | | | |
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Title:
|
RTL POWER ANALYSIS USING GATE-LEVEL CELL POWER MODELS
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|
|
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Patent #:
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|
Issue Dt:
|
05/22/2007
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Application #:
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10627933
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Filing Dt:
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07/25/2003
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Publication #:
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Pub Dt:
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05/06/2004
| | | | |
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Title:
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CIRCUIT OPTIMIZATION FOR MINIMUM PATH TIMING VIOLATIONS
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|
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Patent #:
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|
Issue Dt:
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10/03/2006
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Application #:
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10739659
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Filing Dt:
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12/17/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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CURRENT SCHEDULING SYSTEM AND METHOD FOR OPTIMIZING MULTI-THRESHOLD CMOS DESIGNS
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10926660
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Filing Dt:
|
08/25/2004
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|
Publication #:
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Pub Dt:
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02/03/2005
| | | | |
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Title:
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VECTORLESS INSTANTANEOUS CURRENT ESTIMATION
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