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Reel/Frame:026145/0477   Pages: 3
Recorded: 04/18/2011
Attorney Dkt #:852763.503C1
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
02/19/2013
Application #:
13022419
Filing Dt:
02/07/2011
Publication #:
Pub Dt:
08/04/2011
Title:
CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER
Assignor
1
Exec Dt:
02/22/2011
Assignee
1
VIA C. OLIVETTI, 2
AGRATE BRIANZA, ITALY 20041
Correspondence name and address
ROBERT IANNUCCI
701 FIFTH AVENUE
SUITE 5400
SEATTLE, WA 98104

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