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Total properties:
17
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10277700
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Filing Dt:
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10/22/2002
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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METHOD AND APPARATUS FOR VERIFICATION OF DIGITAL ARITHMETIC CIRCUITS BY MEANS OF AN EQUIVALENCE COMPARISON
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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10525999
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Filing Dt:
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11/28/2005
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Publication #:
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Pub Dt:
|
05/11/2006
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Title:
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METHOD AND DEVICE FOR VERIFYING DIGITAL CIRCUITS
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10719818
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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06/17/2004
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Title:
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METHOD AND APPARATUS FOR DETERMINING THE MINIMUM OR MAXIMUM SWITCHING ACTIVITY OF A DIGITAL CIRCUIT
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10901558
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Filing Dt:
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07/29/2004
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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METHOD AND DEVICE FOR CIRCUIT VERIFICATION
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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11177203
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Filing Dt:
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07/07/2005
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Publication #:
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Pub Dt:
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03/23/2006
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Title:
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METHOD AND APPARATUS FOR LOCATING CIRCUIT DEVIATIONS
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Patent #:
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Issue Dt:
|
08/04/2009
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Application #:
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11459433
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Filing Dt:
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07/24/2006
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Publication #:
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Pub Dt:
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09/27/2007
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Title:
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METHOD FOR THE DETERMINATION OF THE QUALITY OF A SET OF PROPERTIES, USABLE FOR THE VERIFICATION AND SPECIFICATION OF CIRCUITS
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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11876903
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Filing Dt:
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10/23/2007
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Publication #:
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Pub Dt:
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04/24/2008
| | | | |
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Title:
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SYSTEM AND METHOD FOR VERIFICATION AND GENERATION OF TIMING EXCEPTIONS
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|
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Patent #:
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Issue Dt:
|
01/22/2013
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Application #:
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12275557
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Filing Dt:
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11/21/2008
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Publication #:
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Pub Dt:
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08/13/2009
| | | | |
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Title:
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EQUIVALENCE VERIFICATION BETWEEN TRANSACTION LEVEL MODELS AND RTL AT THE EXAMPLE TO PROCESSORS
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12488672
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Filing Dt:
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06/22/2009
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
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Title:
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METHOD FOR DETERMINING THE QUALITY OF A QUANTITY OF PROPERTIES, TO BE EMPLOYED FOR VERIFYING AND SPECIFYING CIRCUITS
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|
|
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Patent #:
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Issue Dt:
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04/15/2014
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Application #:
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13457240
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Filing Dt:
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04/26/2012
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Publication #:
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Pub Dt:
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01/17/2013
| | | | |
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Title:
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DIGITAL CIRCUIT VERIFICATION MONITOR
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|
|
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Patent #:
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|
Issue Dt:
|
05/12/2015
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Application #:
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14228921
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Filing Dt:
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03/28/2014
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Publication #:
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Pub Dt:
|
07/31/2014
| | | | |
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Title:
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DIGITAL CIRCUIT VERIFICATION MONITOR
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/17/2016
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Application #:
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14261671
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Filing Dt:
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04/25/2014
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Publication #:
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Pub Dt:
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10/30/2014
| | | | |
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Title:
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Cloud-Basd Digital Verification System and Method
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|
|
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Patent #:
|
|
Issue Dt:
|
08/04/2020
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Application #:
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15790339
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Filing Dt:
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10/23/2017
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Publication #:
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Pub Dt:
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04/25/2019
| | | | |
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Title:
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Method of Selecting a Prover
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|
|
|
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Patent #:
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|
Issue Dt:
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12/06/2022
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Application #:
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16620622
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Filing Dt:
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12/09/2019
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Publication #:
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Pub Dt:
|
06/25/2020
| | | | |
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Title:
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SYSTEM AND METHOD FOR FORMAL FAULT PROPAGATION ANALYSIS
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|
|
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Patent #:
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|
Issue Dt:
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10/26/2021
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Application #:
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16920484
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Filing Dt:
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07/03/2020
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Publication #:
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Pub Dt:
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01/07/2021
| | | | |
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Title:
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METHOD OF CHECKING EQUIVALENCE BETWEEN A FIRST DESIGN COMPRISING A SHIFT REGISTER LOGIC SRL CHAIN AND A SECOND DESIGN
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|
|
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Patent #:
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|
Issue Dt:
|
02/15/2022
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Application #:
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17011204
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Filing Dt:
|
09/03/2020
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Publication #:
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Pub Dt:
|
03/04/2021
| | | | |
|
Title:
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Method to Perform Hardware Safety Analysis without Fault Simulation
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/14/2023
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Application #:
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17899210
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Filing Dt:
|
08/30/2022
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Publication #:
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|
Pub Dt:
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12/29/2022
| | | | |
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Title:
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SYSTEM AND METHOD FOR FORMAL FAULT PROPAGATION ANALYSIS
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