Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 065880/0480 | |
| Pages: | 5 |
| | Recorded: | 12/15/2023 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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12053761
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Filing Dt:
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03/24/2008
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Publication #:
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Pub Dt:
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09/24/2009
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Title:
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SELECTIVE INTERCONNECT TRANSACTION CONTROL FOR CACHE COHERENCY MAINTENANCE
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12112508
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Filing Dt:
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04/30/2008
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Publication #:
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Pub Dt:
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11/05/2009
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Title:
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CACHE COHERENCY PROTOCOL IN A DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12201216
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Filing Dt:
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08/29/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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CACHE SNOOP LIMITING WITHIN A MULTIPLE MASTER DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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02/14/2012
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Application #:
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12437115
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Filing Dt:
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05/07/2009
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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PROCESSING OF COHERENT AND INCOHERENT ACCESSES AT A UNIFORM CACHE
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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12886641
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Filing Dt:
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09/21/2010
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Publication #:
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Pub Dt:
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03/22/2012
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Title:
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DATA PROCESSOR FOR PROCESSING DECORATED INSTRUCTIONS WITH CACHE BYPASS
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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12915198
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Filing Dt:
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10/29/2010
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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DATA PROCESSING SYSTEM HAVING SELECTIVE INVALIDATION OF SNOOP REQUESTS AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/13/2016
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Application #:
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13570843
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Filing Dt:
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08/09/2012
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Publication #:
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Pub Dt:
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02/13/2014
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Title:
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Interrupt Priority Management Using Partition-Based Priority Blocking Processor Registers
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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13570874
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Filing Dt:
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08/09/2012
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Publication #:
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Pub Dt:
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02/13/2014
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Title:
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Processor Interrupt Interface with Interrupt Partitioning and Virtualization Enhancements
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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13989280
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Filing Dt:
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05/23/2013
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Publication #:
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Pub Dt:
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09/12/2013
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Title:
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METHOD AND APPARATUS FOR MANAGING POWER IN A MULTI-CORE PROCESSOR
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Patent #:
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Issue Dt:
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09/20/2016
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Application #:
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14495209
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Filing Dt:
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09/24/2014
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Publication #:
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Pub Dt:
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03/24/2016
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Title:
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Piggy-Back Snoops For Non-Coherent Memory Transactions Within Distributed Processing Systems
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Assignee
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| THE HYDE BUILDING, SUITE 23 |
| THE PARK, CARRICKMINES |
| DUBLIN, IRELAND 18 |
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Correspondence name and address
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ANTONIO PAPAGEORGIOU
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230 PARK AVENUE, 4TH FLOOR WEST
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C/O LOMBARD & GELIEBTER LLP
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NEW YORK, NY 10169
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