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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:030740/0481   Pages: 226
Recorded: 07/03/2013
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 77
1
Patent #:
Issue Dt:
04/04/1995
Application #:
08099606
Filing Dt:
07/30/1993
Title:
REDUNDANCY ELEMENT CHECK IN IC MEMORY WITHOUT PROGRAMMING SUBSTITUTION OF REDUNDANT ELEMENTS
2
Patent #:
Issue Dt:
12/27/1994
Application #:
08099947
Filing Dt:
07/30/1993
Title:
DISABLING SENSE AMPLIFIER
3
Patent #:
Issue Dt:
11/05/1996
Application #:
08114747
Filing Dt:
08/31/1993
Title:
DISTRIBUTED NOR TAG MATCH APPARATUS
4
Patent #:
Issue Dt:
03/28/1995
Application #:
08114749
Filing Dt:
08/31/1993
Title:
PRECHARGE DEVICE FOR AN INTEGRATED CIRCUIT INTERNAL BUS
5
Patent #:
Issue Dt:
03/07/1995
Application #:
08129257
Filing Dt:
09/30/1993
Title:
LATCH CONTROLLED OUTPUT DRIVER
6
Patent #:
Issue Dt:
05/23/1995
Application #:
08129763
Filing Dt:
09/30/1993
Title:
EDGE TRANSITION DETECTION DISABLE CIRCUIT TO ALTER MEMORY DEVICE OPERATING CHARACTERISTICS
7
Patent #:
Issue Dt:
08/08/1995
Application #:
08160608
Filing Dt:
11/30/1993
Title:
STATIC TEST MODE NOISE FILTER
8
Patent #:
Issue Dt:
08/08/2000
Application #:
08172848
Filing Dt:
12/22/1993
Title:
METHOD AND DEVICE FOR ACQUIRING REDUNDANCY INFORMATION FROM A PACKAGED MEMORY CHIP
9
Patent #:
Issue Dt:
10/22/1996
Application #:
08172853
Filing Dt:
12/22/1993
Title:
DATA COMPARING SENSE AMPLIFIER
10
Patent #:
Issue Dt:
11/10/1998
Application #:
08172854
Filing Dt:
12/22/1993
Title:
STRESS TEST MODE
11
Patent #:
Issue Dt:
11/19/1996
Application #:
08173197
Filing Dt:
12/22/1993
Title:
STATIC MEMORY LONG WRITE TEST
12
Patent #:
Issue Dt:
11/26/1996
Application #:
08189589
Filing Dt:
01/31/1994
Title:
METHOD AND APPARATUS FOR PROGRAMMING SIGNAL TIMING
13
Patent #:
Issue Dt:
05/14/1996
Application #:
08220976
Filing Dt:
03/31/1994
Title:
INTEGRATED CIRCUIT WITH FUSE CIRCUITRY SIMULATING FUSE BLOWING
14
Patent #:
Issue Dt:
06/25/1996
Application #:
08235161
Filing Dt:
04/29/1994
Title:
STRUCTURE CAPABLE OF SIMULTANEOUSLY TESTING REDUNDANT AND NON-REDUNDANT MEMORY ELEMENTS DURING STRESS TESTING OF AN INTEGRATED CIRCUIT MEMORY DEVICE
15
Patent #:
Issue Dt:
10/03/1995
Application #:
08267666
Filing Dt:
06/29/1994
Title:
CIRCUIT WHICH PROVIDES POWER ON RESET DISABLE DURING A TEST MODE
16
Patent #:
Issue Dt:
12/10/1996
Application #:
08267667
Filing Dt:
06/29/1994
Title:
LONG WRITE TEST
17
Patent #:
Issue Dt:
11/09/1999
Application #:
08282047
Filing Dt:
07/29/1994
Title:
TEST MODE CONTROL CIRCUIT OF AN INTEGRATED CIRCUIT DEVICE
18
Patent #:
Issue Dt:
12/31/1996
Application #:
08282177
Filing Dt:
07/29/1994
Title:
VARIABLE INPUT THRESHOLD ADJUSTMENT
19
Patent #:
Issue Dt:
10/15/1996
Application #:
08288334
Filing Dt:
08/10/1994
Title:
APPARATUS AND METHOD FOR ENABLING A BUS DRIVER WHEN A DATA SIGNAL IS VALID
20
Patent #:
Issue Dt:
03/26/1996
Application #:
08315337
Filing Dt:
09/30/1994
Title:
FULL MEMORY CHIP LONG WRITE TEST MODE
21
Patent #:
Issue Dt:
02/27/1996
Application #:
08316087
Filing Dt:
09/30/1994
Title:
PRE-CHARGED EXCLUSIONARY WIRED-CONNECTED PROGRAMMED REDUNDANT SELECT
22
Patent #:
Issue Dt:
03/11/1997
Application #:
08331699
Filing Dt:
10/31/1994
Title:
CIRCUIT STRUCTURE AND METHOD FOR STRESS TESTING OF BIT LINES
23
Patent #:
Issue Dt:
05/14/1996
Application #:
08331892
Filing Dt:
10/31/1994
Title:
LOW CURRENT DIFFERENTIAL LEVEL SHIFTER
24
Patent #:
Issue Dt:
10/22/1996
Application #:
08357664
Filing Dt:
12/16/1994
Title:
CIRCUIT FOR PROVIDING A COMPENSATED BIAS VOLTAGE
25
Patent #:
Issue Dt:
01/14/1997
Application #:
08359397
Filing Dt:
12/20/1994
Title:
OUTPUT DRIVER CIRCUITRY WITH SELECTIVE LIMITED OUTPUT HIGH VOLTAGE
26
Patent #:
Issue Dt:
01/28/1997
Application #:
08359926
Filing Dt:
12/20/1994
Title:
VOLTAGE REFERENCE CIRCUIT HAVING A THRESHOLD VOLTAGE SHIFT
27
Patent #:
Issue Dt:
12/03/1996
Application #:
08359927
Filing Dt:
12/20/1994
Title:
ADJUSTABLE CURRENT SOURCE
28
Patent #:
Issue Dt:
12/31/1996
Application #:
08360227
Filing Dt:
12/20/1994
Title:
DYNAMICALLY CONTROLLED VOLTAGE REFERENCE CIRCUIT
29
Patent #:
Issue Dt:
01/21/1997
Application #:
08360228
Filing Dt:
12/20/1994
Title:
OUTPUT DRIVER CIRCUITRY WITH LIMITED OUTPUT HIGH VOLTAGE
30
Patent #:
Issue Dt:
08/20/1996
Application #:
08360229
Filing Dt:
12/20/1994
Title:
VOLTAGE REFERENCE CIRCUIT USING AN OFFSET COMPENSATING CURRENT SOURCE
31
Patent #:
Issue Dt:
11/26/1996
Application #:
08362187
Filing Dt:
12/22/1994
Title:
POST-FABRICATION SELECTABLE REGISTERED AND NON-REGISTERED MEMORY
32
Patent #:
Issue Dt:
11/19/1996
Application #:
08414103
Filing Dt:
03/31/1995
Title:
VOLTAGE REGULATOR FOR AN OUTPUT DRIVER WITH REDUCED OUTPUT IMPEDANCE
33
Patent #:
Issue Dt:
11/05/1996
Application #:
08438349
Filing Dt:
05/10/1995
Title:
APPARATUS AND METHOD FOR MAPPING A REDUNDANT MEMORY COLUMN TO A DEFECTIVE MEMORY COLUMN
34
Patent #:
Issue Dt:
11/12/1996
Application #:
08438903
Filing Dt:
05/10/1995
Title:
APPARATUS AND METHOD FOR MAPPING A REDUNDANT MEMORY COLUMN TO A DEFECTIVE MEMORY COLUMN
35
Patent #:
Issue Dt:
06/17/1997
Application #:
08464551
Filing Dt:
06/05/1995
Title:
CIRCUIT FOR PROVIDING A BIAS VOLTAGE COMPENSATED FOR P-CHANNEL TRANSISTOR VARIATIONS
36
Patent #:
Issue Dt:
06/16/1998
Application #:
08484491
Filing Dt:
06/07/1995
Title:
CIRCUIT AND METHOD FOR BIASING BIT LINES
37
Patent #:
Issue Dt:
07/15/1997
Application #:
08509211
Filing Dt:
07/31/1995
Title:
STRUCTURE FOR DESELECTING BROKEN SELECT LINES IN MEMORY ARRAYS
38
Patent #:
Issue Dt:
03/04/1997
Application #:
08509351
Filing Dt:
07/31/1995
Title:
COLUMN REDUNDANCY OF A MULTIPLE BLOCK MEMORY ARCHITECTURE
39
Patent #:
Issue Dt:
05/27/1997
Application #:
08519075
Filing Dt:
08/24/1995
Title:
CIRCUITRY AND METHODOLOGY TO TEST SINGLE BIT FAILURES OF INTEGRATED CIRCUIT MEMORY DEVICES
40
Patent #:
Issue Dt:
05/13/1997
Application #:
08521800
Filing Dt:
08/31/1995
Title:
WRITE CONTROLLED ADDRESS BUFFER
41
Patent #:
Issue Dt:
11/07/2000
Application #:
08587709
Filing Dt:
01/19/1996
Title:
TEST MODE ACTIVATION AND DATA OVERRIDE
42
Patent #:
Issue Dt:
01/26/1999
Application #:
08587711
Filing Dt:
01/19/1996
Title:
CIRCUIT AND METHOD FOR SETTING THE TIME DURATION OF A WRITE TO A MEMORY CELL
43
Patent #:
Issue Dt:
09/01/1998
Application #:
08587728
Filing Dt:
01/19/1996
Title:
CLOCKED SENSE AMPLIFIER WITH WORDLINE TRACKING
44
Patent #:
Issue Dt:
07/21/1998
Application #:
08588648
Filing Dt:
01/19/1996
Title:
SWITCHING MASTER SLAVE CIRCUIT
45
Patent #:
Issue Dt:
08/12/1997
Application #:
08588662
Filing Dt:
01/19/1996
Title:
WRITE PASS THROUGH CIRCUIT
46
Patent #:
Issue Dt:
12/23/1997
Application #:
08588730
Filing Dt:
01/19/1996
Title:
PIPELINED CHIP ENABLE CONTROL CIRCUITRY AND METHODOLOGY
47
Patent #:
Issue Dt:
12/01/1998
Application #:
08588762
Filing Dt:
01/19/1996
Title:
DATA-INPUT DEVICE FOR GENERATING TEST SIGNALS ON BIT AND BIT-COMPLEMENT LINES
48
Patent #:
Issue Dt:
09/01/1998
Application #:
08588988
Filing Dt:
01/19/1996
Title:
OUTPUT DRIVER CIRCUITRY HAVING A SINGLE SLEW RATE RESISTOR
49
Patent #:
Issue Dt:
04/08/1997
Application #:
08589024
Filing Dt:
01/19/1996
Title:
LOW-POWER READ CIRCUIT AND METHOD FOR CONTROLLING A SENSE AMPLIFIER
50
Patent #:
Issue Dt:
04/28/1998
Application #:
08589141
Filing Dt:
01/19/1996
Title:
WRITE DRIVER HAVING A TEST FUNCTION
51
Patent #:
Issue Dt:
09/15/1998
Application #:
08710357
Filing Dt:
09/17/1996
Title:
INTEGRATED CIRCUIT THAT SUPPORTS AND METHOD FOR WAFER-LEVEL TESTING
52
Patent #:
Issue Dt:
03/14/2000
Application #:
08758587
Filing Dt:
11/27/1996
Title:
CIRCUIT AND METHOD FOR SELECTING A SIGNAL
53
Patent #:
Issue Dt:
06/09/1998
Application #:
08771642
Filing Dt:
12/21/1996
Title:
EXTERNAL WRITE PULSE CONTROL METHOD AND STRUCTURE
54
Patent #:
Issue Dt:
09/28/1999
Application #:
08844696
Filing Dt:
04/25/1997
Title:
SENSE AMPLIFIER CONTROL OF A MEMORY DEVICE
55
Patent #:
Issue Dt:
09/28/1999
Application #:
08966042
Filing Dt:
11/07/1997
Title:
STRUCTURE FOR DESELECTIVE BROKEN SELECT LINES IN MEMORY ARRAYS
56
Patent #:
Issue Dt:
11/30/1999
Application #:
09087399
Filing Dt:
05/29/1998
Title:
CIRCUIT AND METHOD FOR READING A MEMORY CELL
57
Patent #:
Issue Dt:
08/31/1999
Application #:
09183231
Filing Dt:
10/30/1998
Title:
METHOD AND STRUCTURE FOR ENHANCING THE ACCESS TIME OF INTEGRATED CIRCUIT MEMORY DEVICES
58
Patent #:
Issue Dt:
06/27/2000
Application #:
09183451
Filing Dt:
10/30/1998
Title:
STRESS TEST MODE ENTRY AT POWER UP FOR LOW/ZERO POWER MEMORIES
59
Patent #:
Issue Dt:
03/07/2000
Application #:
09183589
Filing Dt:
10/30/1998
Title:
CONTROL CIRCUIT FOR TERMINATING A MEMORY ACCESS CYCLE IN A MEMORY BLOCK OF AN ELECTRONIC STORAGE DEVICE
60
Patent #:
Issue Dt:
03/21/2000
Application #:
09183840
Filing Dt:
10/30/1998
Title:
INITIALIZATION FOR FUSE CONTROL
61
Patent #:
Issue Dt:
02/11/2003
Application #:
09205598
Filing Dt:
12/04/1998
Publication #:
Pub Dt:
06/06/2002
Title:
PIPELINED NON-BLOCKING LEVEL TWO CACHE SYSTEM WITH INHERENT TRANSACTION COLLISION-AVOIDANCE
62
Patent #:
Issue Dt:
09/12/2000
Application #:
09217321
Filing Dt:
12/21/1998
Title:
APPARATUS AND METHOD FOR SWITCHING BETWEEN TWO POWER SUPPLIES OF AN INTEGRATED CIRCUIT
63
Patent #:
Issue Dt:
07/04/2000
Application #:
09217323
Filing Dt:
12/21/1998
Title:
METHOD AND APPARATUS FOR INCREASING COMPARATOR GAIN WITHOUT AFFECTING STANDBY CURRENT
64
Patent #:
Issue Dt:
08/13/2002
Application #:
09335024
Filing Dt:
06/17/1999
Title:
COMMUNICATIONS SYSTEM AND METHOD FOR REDUCING THE EFFECTS OF TRANSMITTER NON-LINEAR DISTORTION ON A RECEIVED SIGNAL
65
Patent #:
Issue Dt:
08/28/2001
Application #:
09476036
Filing Dt:
12/31/1999
Title:
REFERENCE VOLTAGE ASJUSTMENT
66
Patent #:
Issue Dt:
10/15/2002
Application #:
09568201
Filing Dt:
05/05/2000
Title:
POWER SUPPLY SWITCH REFERENCE CIRCUITRY
67
Patent #:
Issue Dt:
07/15/2003
Application #:
09653495
Filing Dt:
08/31/2000
Title:
INTEGRATED VOLATILE AND NON-VOLATILE MEMORY
68
Patent #:
Issue Dt:
12/17/2002
Application #:
09895491
Filing Dt:
06/29/2001
Publication #:
Pub Dt:
01/02/2003
Title:
CONTENT ADDRESSABLE MEMORY (CAM) WITH BATTERY BACK-UP
69
Patent #:
Issue Dt:
04/22/2003
Application #:
09922044
Filing Dt:
08/02/2001
Publication #:
Pub Dt:
02/06/2003
Title:
DUAL BANK FLASH MEMORY DEVICE AND METHOD
70
Patent #:
Issue Dt:
05/13/2003
Application #:
09922068
Filing Dt:
08/02/2001
Publication #:
Pub Dt:
02/06/2003
Title:
REDUNDANCY CIRCUIT AND METHOD FOR FLASH MEMORY DEVICES
71
Patent #:
Issue Dt:
11/23/2004
Application #:
10190917
Filing Dt:
07/08/2002
Publication #:
Pub Dt:
01/08/2004
Title:
SINGLE ENDED OUTPUT SENSE AMPLIFIER CIRCUIT WITH REDUCED POWER CONSUMPTION AND NOISE
72
Patent #:
Issue Dt:
05/29/2007
Application #:
10783935
Filing Dt:
02/20/2004
Publication #:
Pub Dt:
07/14/2005
Title:
TAMPER MEMORY CELL
73
Patent #:
Issue Dt:
02/06/2007
Application #:
10788581
Filing Dt:
02/27/2004
Publication #:
Pub Dt:
11/11/2004
Title:
USER RAM FLASH CLEAR
74
Patent #:
Issue Dt:
04/24/2007
Application #:
10999751
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/23/2005
Title:
RESET INITIALIZATION
75
Patent #:
Issue Dt:
05/06/2008
Application #:
11012533
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
06/23/2005
Title:
VOLTAGE TRANSLATING CONTROL STRUCTURE
76
Patent #:
Issue Dt:
10/02/2007
Application #:
11012712
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
06/23/2005
Title:
RESET CIRCUIT
77
Patent #:
Issue Dt:
02/19/2008
Application #:
11013123
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
06/23/2005
Title:
ESD BONDING PAD
Assignor
1
Exec Dt:
05/23/2012
Assignee
1
8000 SO. FEDERAL WAY
BOISE, IDAHO 83716-9632
Correspondence name and address
MARK V. MULLER
SCHWEGMAN, LUNDBERG & WOESSNER, P.A.
P.O. BOX 2938
MINNEAPOLIS, MN 55402--0938

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