Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 020218/0486 | |
| Pages: | 4 |
| | Recorded: | 12/10/2007 | | |
| Attorney Dkt #: | ID 059607 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
11
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09209532
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Filing Dt:
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12/11/1998
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Title:
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METHOD AND APPARATUS FOR PROVIDING INSTRUCTION STREAMS TO A PROCESSING DEVICE
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09209542
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Filing Dt:
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12/11/1998
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Title:
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RECONFIGURABLE PROCESSOR DEVICES
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09341565
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Filing Dt:
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07/13/1999
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Title:
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FIELD PROGRAMMABLE PROCESSOR DEVICES
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09341566
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Filing Dt:
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07/13/1999
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Title:
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FIELD PROGRAMMABLE PROCESSOR ARRAYS
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09555624
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Filing Dt:
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06/01/2000
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Title:
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IMPLEMENTATION OF MULTIPLIERS IN PROGRAMMABLE ARRAYS
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09761768
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Filing Dt:
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01/18/2001
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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INKJET PRINTHEAD WITH HIGH NOZZLE TO PRESSURE ACTIVATOR RATIO
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09891736
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Filing Dt:
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06/25/2001
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Publication #:
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Pub Dt:
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11/01/2001
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Title:
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FIELD PROGRAMMABLE PROCESSOR ARRAYS
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10224093
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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LOW-POWER VOLTAGE MODULATION CIRCUIT FOR PASS DEVICES
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10337596
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Filing Dt:
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01/06/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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METHOD AND APPARATUS FOR VARYING INSTRUCTION STREAMS PROVIDED TO A PROCESSING DEVICE USING MASKS
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10628906
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Filing Dt:
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07/28/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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METHODS AND SYSTEMS FOR REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR CIRCUITS
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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11006974
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Filing Dt:
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12/07/2004
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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METHODS AND SYSTEMS FOR REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR CIRCUITS
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Assignee
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| 1006, OAZA-KADOMA |
| KADOMA-SHI, OSAKA, JAPAN |
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Correspondence name and address
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DAVID J. CUSHING
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2100 PENNSYLVANIA AVENUE, N.W.
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WASHINGTON, DC 20037
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