Patent Assignment Details
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Reel/Frame: | 032911/0487 | |
| Pages: | 7 |
| | Recorded: | 05/16/2014 | | |
Attorney Dkt #: | 2013-0870 / 24061.2622 |
Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME FROM TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD TO TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. PREVIOUSLY RECORDED ON REEL 032848 FRAME 0080. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTION OF THE ASSIGNEE NAME ON THE NOTICE OF RECORDATION TO TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY, LTD.. |
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Total properties:
1
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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14253282
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Filing Dt:
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04/15/2014
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Publication #:
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Pub Dt:
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10/15/2015
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Title:
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Method of Fabricating an Integrated Circuit with Block Dummy for Optimized Pattern Density Uniformity
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Assignee
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NO. 8, LI-HSIN RD. 6 |
SCIENCE-BASED INDUSTRIAL PARK |
HSIN-CHU, TAIWAN 300-77 |
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Correspondence name and address
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HAYNES AND BOONE, LLP (50833)
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2323 VICTORY AVENUE
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SUITE 700
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DALLAS, TX 75219
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