Patent Assignment Details
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Reel/Frame: | 015850/0490 | |
| Pages: | 17 |
| | Recorded: | 09/27/2004 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10952222
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Filing Dt:
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09/27/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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CONNECTING VERILOG-AMS AND VHDL-AMS COMPONENTS IN A MIXED-LANGUAGE MIXED-SIGNAL DESIGN
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Assignee
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2655 SEELY AVENUE, BUILDING 5 |
SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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MORRISON & FOERSTER, LLP
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THOMAS CHAN
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755 PAGE MILL ROAD
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PALO ALTO, CA 94304
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