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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	067305/0491			Pages:	18
		Recorded:	05/02/2024
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 56

Patent #:	6949801	Issue Dt:	09/27/2005	Application #:	10669825	Filing Dt:	09/23/2003
Publication #:	US20040058508	Pub Dt:	03/25/2004
Title:	DUAL TRENCH ISOLATION USING SINGLE CRITICAL LITHOGRAPHIC PATTERNING

Patent #:	7312490	Issue Dt:	12/25/2007	Application #:	11096390	Filing Dt:	03/31/2005
Publication #:	US20060223262	Pub Dt:	10/05/2006
Title:	VERTICAL MEMORY DEVICE AND METHOD

Patent #:	7913003	Issue Dt:	03/22/2011	Application #:	11361227	Filing Dt:	02/24/2006
Publication #:	US20070204126	Pub Dt:	08/30/2007
Title:	RECLAIM ALGORITHM FOR FAST EDITS IN A NONVOLATILE FILE SYSTEM

Patent #:	9086893	Issue Dt:	07/21/2015	Application #:	11377332	Filing Dt:	03/15/2006
Publication #:	US20130042048	Pub Dt:	02/14/2013
Title:	Techniques to store configuration information in an option read-only memory

Patent #:	NONE	Issue Dt:		Application #:	11618652	Filing Dt:	12/29/2006
Publication #:	US20080158986	Pub Dt:	07/03/2008
Title:	FLASH MEMORY AND ASSOCIATED METHODS FOR READING AND WRITING

Patent #:	8161343	Issue Dt:	04/17/2012	Application #:	11778649	Filing Dt:	07/17/2007
Publication #:	US20090024903	Pub Dt:	01/22/2009
Title:	NIBBLE ENCODING FOR IMPROVED RELIABILITY OF NON-VOLATILE MEMORY

Patent #:	NONE	Issue Dt:		Application #:	12629992	Filing Dt:	12/03/2009
Publication #:	US20110133266	Pub Dt:	06/09/2011
Title:	Flash Memory Having a Floating Gate in the Shape of a Curved Section

Patent #:	NONE	Issue Dt:		Application #:	13189683	Filing Dt:	07/25/2011
Publication #:	US20120191898	Pub Dt:	07/26/2012
Title:	DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLASH FUNCTIONS

Patent #:	NONE	Issue Dt:		Application #:	13431772	Filing Dt:	03/27/2012
Publication #:	US20120181705	Pub Dt:	07/19/2012
Title:	PITCH DIVISION PATTERNING TECHNIQUES

Patent #:	9030885	Issue Dt:	05/12/2015	Application #:	14549785	Filing Dt:	11/21/2014
Publication #:	US20150078088	Pub Dt:	03/19/2015
Title:	EXTENDED SELECT GATE LIFETIME

Patent #:	NONE	Issue Dt:		Application #:	15479224	Filing Dt:	04/04/2017
Publication #:	US20170269837	Pub Dt:	09/21/2017
Title:	USING COUNTERS AND A TABLE TO PROTECT DATA IN A STORAGE DEVICE

Patent #:	NONE	Issue Dt:		Application #:	17107679	Filing Dt:	11/30/2020
Publication #:	US20220172784	Pub Dt:	06/02/2022
Title:	MEMORY CELL SENSING CIRCUIT WITH ADJUSTED BIAS FROM PRE-BOOST OPERATION

Patent #:	NONE	Issue Dt:		Application #:	17112401	Filing Dt:	12/04/2020
Publication #:	US20210118510	Pub Dt:	04/22/2021
Title:	READ LATENCY REDUCTION FOR PARTIALLY-PROGRAMMED BLOCK OF NON-VOLATILE MEMORY

Patent #:	NONE	Issue Dt:		Application #:	17123451	Filing Dt:	12/16/2020
Publication #:	US20220189987	Pub Dt:	06/16/2022
Title:	VERTICAL CHANNEL WITH CONDUCTIVE STRUCTURES TO IMPROVE STRING CURRENT

Patent #:	NONE	Issue Dt:		Application #:	17133834	Filing Dt:	12/24/2020
Publication #:	US20210141703	Pub Dt:	05/13/2021
Title:	PERSISTENT DATA STRUCTURE TO TRACK AND MANAGE SSD DEFECTS

Patent #:	NONE	Issue Dt:		Application #:	17134010	Filing Dt:	12/24/2020
Publication #:	US20220208286	Pub Dt:	06/30/2022
Title:	DYNAMIC DETECTION AND DYNAMIC ADJUSTMENT OF SUB-THRESHOLD SWING IN A MEMORY CELL SENSING CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	17202133	Filing Dt:	03/15/2021
Publication #:	US20220293193	Pub Dt:	09/15/2022
Title:	NAND SENSING CIRCUIT AND TECHNIQUE FOR READ-DISTURB MITIGATION

Patent #:	NONE	Issue Dt:		Application #:	17202137	Filing Dt:	03/15/2021
Publication #:	US20220293194	Pub Dt:	09/15/2022
Title:	MODULATION OF SOURCE VOLTAGE IN NAND-FLASH ARRAY READ

Patent #:	NONE	Issue Dt:		Application #:	17212792	Filing Dt:	03/25/2021
Publication #:	US20220310160	Pub Dt:	09/29/2022
Title:	SIMULTANEOUS PROGRAMMING OF MULTIPLE SUB-BLOCKS IN NAND MEMORY STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	17236651	Filing Dt:	04/21/2021
Publication #:	US20220343982	Pub Dt:	10/27/2022
Title:	STAGGERED ACTIVE BITLINE SENSING

Patent #:	11282550	Issue Dt:	03/22/2022	Application #:	17253573	Filing Dt:	12/17/2020
Publication #:	US20210134334	Pub Dt:	05/06/2021
Title:	TECHNIQUES TO CALIBRATE AN IMPEDANCE LEVEL

Patent #:	NONE	Issue Dt:		Application #:	17314979	Filing Dt:	05/07/2021
Publication #:	US20220359441	Pub Dt:	11/10/2022
Title:	THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS

Patent #:	NONE	Issue Dt:		Application #:	17321114	Filing Dt:	05/14/2021
Publication #:	US20220366991	Pub Dt:	11/17/2022
Title:	PROGRAM VERIFY PROCESS HAVING PLACEMENT AWARE PRE-PROGRAM VERIFY (PPV) BUCKET SIZE MODULATION

Patent #:	NONE	Issue Dt:		Application #:	17322724	Filing Dt:	05/17/2021
Publication #:	US20220366962	Pub Dt:	11/17/2022
Title:	STAGGERED READ RECOVERY FOR IMPROVED READ WINDOW BUDGET IN A THREE DIMENSIONAL (3D) NAND MEMORY ARRAY

Patent #:	NONE	Issue Dt:		Application #:	17343584	Filing Dt:	06/09/2021
Publication #:	US20220399057	Pub Dt:	12/15/2022
Title:	SPLIT BLOCK ARRAY FOR 3D NAND MEMORY

Patent #:	NONE	Issue Dt:		Application #:	17351803	Filing Dt:	06/18/2021
Publication #:	US20220406646	Pub Dt:	12/22/2022
Title:	3D NAND WITH INTER-WORDLINE AIRGAP

Patent #:	NONE	Issue Dt:		Application #:	17357466	Filing Dt:	06/24/2021
Publication #:	US20220415380	Pub Dt:	12/29/2022
Title:	INDEPENDENT MULTI-PAGE READ OPERATION ENHANCEMENT TECHNOLOGY

Patent #:	NONE	Issue Dt:		Application #:	17375540	Filing Dt:	07/14/2021
Publication #:	US20220415908	Pub Dt:	12/29/2022
Title:	METAL HYBRID CHARGE STORAGE STRUCTURE FOR MEMORY

Patent #:	NONE	Issue Dt:		Application #:	17393877	Filing Dt:	08/04/2021
Publication #:	US20230044991	Pub Dt:	02/09/2023
Title:	PAGE MAP RENUMBERING TO REDUCE ERROR CORRECTION FAILURES AND IMPROVE PROGRAM TIME UNIFORMITY

Patent #:	NONE	Issue Dt:		Application #:	17411899	Filing Dt:	08/25/2021
Publication #:	US20230062668	Pub Dt:	03/02/2023
Title:	LEAN COMMAND SEQUENCE FOR MULTI-PLANE READ OPERATIONS

Patent #:	NONE	Issue Dt:		Application #:	17411919	Filing Dt:	08/25/2021
Publication #:	US20230061293	Pub Dt:	03/02/2023
Title:	DYNAMIC GATE STEPS FOR LAST-LEVEL PROGRAMMING TO IMPROVE WRITE PERFORMANCE

Patent #:	NONE	Issue Dt:		Application #:	17441217	Filing Dt:	09/20/2021
Publication #:	US20220148971	Pub Dt:	05/12/2022
Title:	NON-CONDUCTIVE ETCH STOP STRUCTURES FOR MEMORY APPLICATIONS WITH LARGE CONTACT HEIGHT DIFFERENTIAL

Patent #:	NONE	Issue Dt:		Application #:	17442582	Filing Dt:	09/23/2021
Publication #:	US20220189976	Pub Dt:	06/16/2022
Title:	3D MEMORY DEVICE WITH TOP WORDLINE CONTACT LOCATED IN PROTECTED REGION DURING PLANARIZATION

Patent #:	NONE	Issue Dt:		Application #:	17469634	Filing Dt:	09/08/2021
Publication #:	US20230076831	Pub Dt:	03/09/2023
Title:	3D NAND WITH IO CONTACTS IN ISOLATION TRENCH

Patent #:	NONE	Issue Dt:		Application #:	17475880	Filing Dt:	09/15/2021
Publication #:	US20230082368	Pub Dt:	03/16/2023
Title:	GROUPED GLOBAL WORDLINE DRIVER WITH SHARED BIAS SCHEME

Patent #:	NONE	Issue Dt:		Application #:	17483279	Filing Dt:	09/23/2021
Publication #:	US20230086751	Pub Dt:	03/23/2023
Title:	BLOCK LIST MANAGEMENT FOR WORDLINE START VOLTAGE

Patent #:	NONE	Issue Dt:		Application #:	17544072	Filing Dt:	12/07/2021
Publication #:	US20230163011	Pub Dt:	05/25/2023
Title:	CHUCK WITH NON-FLAT SHAPED SURFACE

Patent #:	NONE	Issue Dt:		Application #:	17545672	Filing Dt:	12/08/2021
Publication #:	US20230178158	Pub Dt:	06/08/2023
Title:	PUMP DISCHARGE SEQUENCE IMPROVEMENTS IN EXTERNAL POWER SUPPLY MODE FOR PULSE RECOVERY PHASES IN NON-VOLATILE MEMORY

Patent #:	NONE	Issue Dt:		Application #:	17549685	Filing Dt:	12/13/2021
Publication #:	US20230139346	Pub Dt:	05/04/2023
Title:	ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTACT CONNECTION

Patent #:	NONE	Issue Dt:		Application #:	17550393	Filing Dt:	12/14/2021
Publication #:	US20230164986	Pub Dt:	05/25/2023
Title:	SELECTIVE REMOVAL OF SIDEWALL MATERIAL FOR 3D NAND INTEGRATION

Patent #:	NONE	Issue Dt:		Application #:	17551018	Filing Dt:	12/14/2021
Publication #:	US20230164987	Pub Dt:	05/25/2023
Title:	3D NAND MEMORY CELL WITH FLAT TRAP BASE PROFILE

Patent #:	NONE	Issue Dt:		Application #:	17558001	Filing Dt:	12/21/2021
Publication #:	US20230200061	Pub Dt:	06/22/2023
Title:	TIER EXPANSION OFFSET

Patent #:	NONE	Issue Dt:		Application #:	17559725	Filing Dt:	12/22/2021
Publication #:	US20230200063	Pub Dt:	06/22/2023
Title:	PARALLEL STAIRCASE 3D NAND

Patent #:	NONE	Issue Dt:		Application #:	17763172	Filing Dt:	03/23/2022
Publication #:	US20220406352	Pub Dt:	12/22/2022
Title:	DUMMY WORDLINE CONTACTS TO IMPROVE ETCH MARGIN OF SEMI-ISOLATED WORDLINES IN STAIRCASE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	17791175	Filing Dt:	07/06/2022
Publication #:	US20230033086	Pub Dt:	02/02/2023
Title:	VARYING CHANNEL WIDTH IN THREE-DIMENSIONAL MEMORY ARRAY

Patent #:	NONE	Issue Dt:		Application #:	17791176	Filing Dt:	07/06/2022
Publication #:	US20230036595	Pub Dt:	02/02/2023
Title:	BLOCK-TO-BLOCK ISOLATION AND DEEP CONTACT USING PILLARS IN A MEMORY ARRAY

Patent #:	NONE	Issue Dt:		Application #:	17825960	Filing Dt:	05/26/2022
Publication #:	US20220284968	Pub Dt:	09/08/2022
Title:	METHOD AND APPARATUS TO MITIGATE HOT ELECTRON READ DISTURBS IN 3D NAND DEVICES

Patent #:	NONE	Issue Dt:		Application #:	17919730	Filing Dt:	10/18/2022
Publication #:	US20230163045	Pub Dt:	05/25/2023
Title:	ORGANIC SPACER FOR INTEGRATED CIRCUITS

Patent #:	NONE	Issue Dt:		Application #:	18002513	Filing Dt:	12/20/2022
Publication #:	US20230232629	Pub Dt:	07/20/2023
Title:	METHOD AND APPARATUS TO MITIGATE WORD LINE STAIRCASE ETCH STOP LAYER THICKNESS VARIATIONS IN 3D NAND DEVICES

Patent #:	NONE	Issue Dt:		Application #:	18047094	Filing Dt:	10/17/2022
Publication #:	US20230065187	Pub Dt:	03/02/2023
Title:	STRUCTURE AND METHOD OF INCREASING SUBTRACTIVE BITLINE AIR GAP HEIGHT

Patent #:	NONE	Issue Dt:		Application #:	18047097	Filing Dt:	10/17/2022
Publication #:	US20230079077	Pub Dt:	03/16/2023
Title:	WORD LINE VOLTAGE DETECTION CIRCUIT FOR ENCHANCED READ OPERATION

Patent #:	NONE	Issue Dt:		Application #:	18148230	Filing Dt:	12/29/2022
Publication #:	US20230215478	Pub Dt:	07/06/2023
Title:	MULTI-PHASE CLOCKING SCHEME FOR A MEMORY DEVICE

Patent #:	NONE	Issue Dt:		Application #:	18235727	Filing Dt:	08/18/2023
Publication #:	US20230395166	Pub Dt:	12/07/2023
Title:	TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORY

Patent #:	NONE	Issue Dt:		Application #:	18235766	Filing Dt:	08/18/2023
Publication #:	US20230402389	Pub Dt:	12/14/2023
Title:	INTEGRATED WORD LINE CONTACT STRUCTURES IN THREE-DIMENSIONAL (3D) MEMORY ARRAY

Patent #:	NONE	Issue Dt:		Application #:	18249635	Filing Dt:	04/19/2023
Publication #:	US20230395729	Pub Dt:	12/07/2023
Title:	MEMORY DEVICES WITH GRADIENT-DOPED CONTROL GATE MATERIAL

Patent #:	NONE	Issue Dt:		Application #:	18367319	Filing Dt:	09/12/2023
Publication #:	US20230422506	Pub Dt:	12/28/2023
Title:	LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING

Assignor

INTEL CORPORATION

Exec Dt:

03/28/2024

Assignee

INTEL NDTM US LLC

2200 MISSION COLLEGE BOULEVARD

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	ANGELA MILLER
	C/O CLARIVATE
	P.O. BOX 5427
	TUCSON, AZ 85703

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