Total properties:
22
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Patent #:
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Issue Dt:
|
09/18/2007
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Application #:
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11301236
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Filing Dt:
|
12/12/2005
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Publication #:
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Pub Dt:
|
02/22/2007
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT
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Patent #:
|
|
Issue Dt:
|
04/29/2008
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Application #:
|
11370738
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Filing Dt:
|
03/07/2006
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Publication #:
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Pub Dt:
|
02/22/2007
| | | | |
Title:
|
DRAM DENSITY ENHANCEMENTS
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Patent #:
|
|
Issue Dt:
|
07/15/2008
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Application #:
|
11431439
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Filing Dt:
|
05/10/2006
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Publication #:
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|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
LOW-POWER CAM
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Patent #:
|
|
Issue Dt:
|
10/21/2008
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Application #:
|
11536524
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Filing Dt:
|
09/28/2006
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Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
SINGLE-POLY NON-VOLATILE MEMORY CELL
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|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
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Application #:
|
11747390
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Filing Dt:
|
05/11/2007
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Publication #:
|
|
Pub Dt:
|
03/27/2008
| | | | |
Title:
|
ONE-TIME-PROGRAMMABLE MEMORY
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Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11845311
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Filing Dt:
|
08/27/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
DRAM WITH HYBRID SENSE AMPLIFIER
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|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11845327
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Filing Dt:
|
08/27/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
DRAM WITH WORD LINE COMPENSATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
12016602
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Filing Dt:
|
01/18/2008
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
RAM WITH TRIM CAPACITORS
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|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12016726
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Filing Dt:
|
01/18/2008
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
DENSE READ-ONLY MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
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Application #:
|
12016738
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Filing Dt:
|
01/18/2008
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Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
MEMORY ROW AND COLUMN REDUNDANCY
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|
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Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
12018860
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Filing Dt:
|
01/24/2008
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Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
DRAM WITH REDUCED POWER CONSUMPTION
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|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
12018996
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Filing Dt:
|
01/24/2008
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
DRAM ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
12019852
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Filing Dt:
|
01/25/2008
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
LOW-POWER CAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
12108258
|
Filing Dt:
|
04/23/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DECODER WITH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12108282
|
Filing Dt:
|
04/23/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
EFFICIENT SENSE COMMAND GENERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12109331
|
Filing Dt:
|
04/24/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
SINGLE-POLY NON-VOLATILE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
12131920
|
Filing Dt:
|
06/02/2008
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Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
EFFICIENT XOR CALCULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12144622
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Filing Dt:
|
06/23/2008
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
BLOCK-BY-BLOCK LEAKAGE CONTROL AND INTERFACE
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|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12163989
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
HYBRID DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12258231
|
Filing Dt:
|
10/24/2008
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
Title:
|
MULTI-PORT SRAM IMPLEMENTED WITH SINGLE-PORT 6-TRANSISTOR MEMORY CELLS COUPLED TO AN INPUT MULTIPLEXER AND AN OUTPUT DEMULTIPLEXER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12326086
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Filing Dt:
|
12/01/2008
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
Title:
|
LEAKAGE CONTROL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12968261
|
Filing Dt:
|
12/14/2010
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
NOR-OR DECODER
|
|